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TSW1250EVM: High-Speed LVDS Deserializer and
1
Introduction
2
Functionality
3
Hardware Configurations
3.1
Power Connections
3.2
Switches and Jumpers
3.3
LEDs
3.4
Input Connections
3.5
Output Connections
3.6
USB I/O Connection
4
Software Installation
5
Graphics User Interface (GUI)
5.1
Toolbar
5.2
Message Window
5.3
Device-Specific Selections
5.4
Test Parameters
5.5
Central Pane Display
6
Schematics and Bill of Materials
6.1
Schematics
6.2
Bill of Materials
7
Circuit Board Layout and Layer Stackup
1
Position of Power Connections
2
Position of Switches and Jumpers
3
Position of LEDs
4
Position of Input, Output, and USB Connections
5
Pinout of Header Posts for Parallel Output Data
6
TSW1250 GUI
7
Time Domain Test
8
Single FFT Test
9
Schematic Diagram Page 1
10
Schematic Diagram Page 2
11
Schematic Diagram Page 3
12
Schematic Diagram Page 4
13
Schematic Diagram Page 5
TSW1250C Layout Top Layer – Signal
14
TSW1250C Layout Layer Two – GND1
15
TSW1250C Layout Layer 3 – PWR1
16
TSW1250C Layout Layer 4 – GND2
17
Windows is a trademark of Microsoft Corporation.
SLOU260F – April 2009 – Revised January 2012
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Copyright © 2009–2012, Texas Instruments Incorporated
SLOU260F – April 2009 – Revised January 2012
Contents
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List of Figures
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TSW1250EVM: High-Speed LVDS Deserializer and Analysis System
User's Guide
Analysis System
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Related Manuals for Texas Instruments TSW1250EVM
Summary of Contents for Texas Instruments TSW1250EVM
- Page 1 TSW1250C Layout Layer 3 – PWR1 ..................TSW1250C Layout Layer 4 – GND2 Windows is a trademark of Microsoft Corporation. SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 2 65536-sample record length from the continuous sample data stream coming from the LVDS interface. The TSW1250EVM includes a UART function that can transfer data to and from a USB interface device on the TSW1250 board. The USB interface device on the TSW1250EVM connects to a personal computer (PC) running Windows™...
- Page 3 Power Connections The TSW1250EVM hardware is designed to operate from a single-supply voltage of greater than 6 Vdc. For convenience, two options can supply power to the TSW1250EVM. A bench power supply can supply power to banana jack connections on the TSW1250EVM, or a laptop-style power module that is included with the TSW1250 hardware can supply power.
- Page 4 Switches and Jumpers 3.2.1 Pushbuttons Four pushbutton switches are mounted on the TSW1250EVM. Two pushbutton switches currently have defined functions; two of the switches are reserved for future use. Switches Description Causes the FPGA to reload its bit file from the FPGA EEPROM.
- Page 5 Select the bit file to be programmed into the FPGA. Always set as the Figure-3. Other settings are for future development. Selects the source of the power supply to the TSW1250EVM. Jump Left sides: Select the external 6-V power module through power jack J7. (Default).
- Page 6 Hardware Configurations www.ti.com LEDs Six LEDs are on the TSW1250EVM to indicate the presence of power and the state of the FPGA. See Figure LED D16 illuminates to indicate the presence of a 6-V power supply to the board. The rest of the LEDs are mainly for internal development reference.
- Page 7 TSW1250EVM and MHR_ADCEVMs. The bit clock runs at a higher multiple of the MHR_ADC sample clock and is used to strobe the serial data into the TSW1250EVM and then deserializes the data. A second clock is provided, called the frame clock or FCLK, that runs at the sample rate and is used to delineate the sample boundaries in the serial data stream.
- Page 8 MHR_ADC parallel data samples can be captured in the TSW1250EVM FIFOs and output to a PC through the USB serial port. The data capture by the FIFOs and TSW1250 user interface is the most convenient way to capture data from an MHR_ADC, but sometimes the continuous stream of data is desirable.
- Page 9 The USB is accessed as a virtual communication port (VCP) and shows up in the Hardware Device Manager as TSW1250. On the TSW1250EVM, the USB port acts as a bridge to UART control of the FPGA. Control of the FPGA is managed by reads and writes to a register map of control registers defined in the design of the FPGA.
- Page 10 4. Repeat the preceding steps for Channel 3. 5. Select Save Measurement to CSV, and choose the items intended to save. The example chooses every item. TSW1250EVM: High-Speed LVDS Deserializer and Analysis System SLOU260F – April 2009 – Revised January 2012 Submit Documentation Feedback Copyright ©...
- Page 11 Default is MSB First, check to change to LSB First UART Baud Rate Default is 460800 bps. Options are available to go to slower rate. SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 12 TSW1250EVM and displays the revision of the FPGA firmware and the type of MHR_ADC interface the TSW1250EVM is expecting to see based on jumper settings J10 and J11. At any time, this initial information can be displayed again by selecting the Reinitialize Instrument option in the Instrument Options tab of the toolbar.
- Page 13 Rectangular can be used to process out this effect to some degree. The FFT record length can be set in the FFT Record Length (NS) input text box. The TSW1250EVM supports FFT record lengths of as much as 65536 samples, or as little as 4096 samples.
- Page 14 RMS value of the samples. Figure 7. Time Domain Test SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 15 Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization noise. SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 16 FFT bins are not included to remove any DC biasing component of the signal. Figure 8. Single FFT Test SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 17 Schematics and Bill of Materials www.ti.com Schematics and Bill of Materials Schematics Figure 9. Schematic Diagram Page 1 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 18 Schematics and Bill of Materials www.ti.com Figure 10. Schematic Diagram Page 2 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 19 Schematics and Bill of Materials www.ti.com Figure 11. Schematic Diagram Page 3 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 20 Schematics and Bill of Materials www.ti.com Figure 12. Schematic Diagram Page 4 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 21 Schematics and Bill of Materials www.ti.com Figure 13. Schematic Diagram Page 5 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 22 J10, J11 HEADER 3 jumper3 22-28-4030 Molex Short pins 1-2 with shunt connector DigiKey # S9000-ND SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 23 TPS76750QPWP TI Provide 6_pwrpad LV7745DEV-200MHz SMD_XTAL_7X5MM_6PI LV7745DEV-200MHz PLETRONICS U11, U13 TPS76733QPWP HTSSOP_20_260x177_2 TPS76733QPWP TI Provide 6_pwrpad SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 24 .875" ALUM Circuit Board Layout and Layer Stackup Figure 14. TSW1250C Layout Top Layer – Signal SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 25 Circuit Board Layout and Layer Stackup www.ti.com Figure 15. TSW1250C Layout Layer Two – GND1 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 26 Circuit Board Layout and Layer Stackup www.ti.com Figure 16. TSW1250C Layout Layer 3 – PWR1 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 27 Circuit Board Layout and Layer Stackup www.ti.com Figure 17. TSW1250C Layout Layer 4 – GND2 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 28 Circuit Board Layout and Layer Stackup www.ti.com Figure 18. TSW1250C Layout Layer 5 – Signal SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 29 Circuit Board Layout and Layer Stackup www.ti.com Figure 19. TSW1250C Layout Layer 6 – Signal SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 30 Circuit Board Layout and Layer Stackup www.ti.com Figure 20. TSW1250C Layout Layer 7 – GND3 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 31 Circuit Board Layout and Layer Stackup www.ti.com Figure 21. TSW1250C Layout Layer 8 – PWR2 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 32 Circuit Board Layout and Layer Stackup www.ti.com Figure 22. TSW1250C Layer 9 – GND4 SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 33 Circuit Board Layout and Layer Stackup www.ti.com Figure 23. TSW1250C Bottom Layer – Signal SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 34 Circuit Board Layout and Layer Stackup www.ti.com Figure 24. Circuit Board Stackup SLOU260F – April 2009 – Revised January 2012 TSW1250EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated...
- Page 35 Any exceptions to this is strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization.
- Page 36 REGULATORY COMPLIANCE INFORMATION (continued) FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
- Page 37 Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjukku-ku, Tokyo, Japan http://www.tij.co.jp 【ご使用にあたっての注】...
- Page 38 FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated...
- Page 39 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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