ZiLOG Z80-AIO Hardware User Manual page 33

Test 13 - Generate Ramp DAC l
This test generates a ramp from a chronological sequence
exercising the DAC to its minimum and maximum values of the
conversion ränge.
and does not imply that monotinicity and linearity can be
measured or accurately observed with Standard laboratory
Test 14 - Generate Ramp DAC 2
This test is the same äs Test 13 and applies to DAC 2.
Test 15 - Bipolar Continuity Test - Pulling Mode
Descr iption
This test checks for missing codes by feeding the analog
Output into the analog input and comparing the conversion
results of the A/D Converter to the data word of the D/A
converter.
LSB of the expected conversion word, then the test will
increment to the next chronological D/A word and perform the
test again. This process is continuecl until the entire ränge
of conversion is tested for that analog input channel.
is again tested in its entirety.
until all analog input channels have been tested.
couse of the test, if a channel fails to match the expected
data word within +1 LSB, the test will respond with the
where channel A may ränge from 0-31 and BCDE and FGHI are
actual and expected data words.
A response of "yes" will repeat the test for the same channel
and data word. A response of "no" will increment the data
word to the next chronological number.
have been exercised, the test will respond with the message
the analog input to the analog Output has been previousiy
described. This test operates by checking the Status word or
conversion complete.
The test is intended for observation only
This process is repeated
"Do you want test repeated?"
The test fixture to juroper
This is known äs Polling Mode.
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After all channels
The