Table of Contents
Advertisement
B61
PCIE_RX2+
PCIe lane #2 Receive+
B62
PCIE_RX2-
PCIe lane #2 Receive-
B63
SDIO_CD# / GPO3
SDIO#0 CardDetect / General Purpose Output 3
B64
PCIE_RX1+
PCIe lane #1 Receive+
B65
PCIE_RX1-
PCIe lane #1 Receive-
B66
WAKE0#
PCI Express Wake Event
B67
WAKE1#
General Purpose Wake Event
B68
PCIE_RX0+
PCIe lane #0 Receive+
B69
PCIE_RX0-
PCIe lane #0 Receive-
B70
GND_23
Power Ground
B71
DDI0_PAIR0+
SDVOB_RED_P
B72
DDI0_PAIR0-
SDVOB_RED_N
B73
DDI0_PAIR1+
SDVOB_GREEN_P
B74
DDI0_PAIR1-
SDVOB_GREEN_N
B75
DDI0_PAIR2+
SDVOB_BLUE_P
B76
DDI0_PAIR2-
SDVOB_BLUE_N
B77
DDI0_PAIR4+
SDVOB_INT_P
B78
DDI0_PAIR4-
SDVOB_INT_N
B79
LVDS_BKLT_EN
Backlight Enable
B80
GND_24
Power Ground
B81
DDI0_PAIR3+
SDVOB_CLKIN_P
B82
DDI0_PAIR3-
SDVOB_CLKIN_N
B83
LVDS_BKLT_CTRL
Backlight Brightness Control
B84
VCC_5V_SBY
+5V Standby
B85
VCC_5V_SBY
+5V Standby
B86
VCC_5V_SBY
+5V Standby
B87
VCC_5V_SBY
+5V Standby
B88
BIOS_DIS1#
Disable Module BIOS.Enable boot from SPI on
Baseboard
B89
DDI0_HPD
Not Connected
B90
GND_25
Power Ground
B91
DDI0_PAIR5+
SDVOB_TVCLKIN_P
B92
DDI0_PAIR5-
SDVOB_TVCLKIN_N
B93
DDI0_PAIR6+
SDVO_STALLP
B94
DDI0_PAIR6-
SDVO_STALLN
B95
DDI0_DDC_AUX_SEL
nc / SDVOB_CTRLCLK (Optional)
B96
RSVD
nc / SDVOB_CTRLDATA(Optional)
B97
SPI_CS#
SPI Chipselect
B98
DDI0_AUX+
SDVOB_CTRLCLK
B99
DDI0_AUX-
SDVOB_CTRLDATA
B100
GND_26
Power Ground
B101
FAN_PWMOUT
Not connected
B102
FAN_TACHIN
Not connected
B103
SLEEP#
Not Connected
B104
VCC_12V_16
12V VCC
B105
VCC_12V_17
12V VCC
B106
VCC_12V_18
12V VCC
B107
VCC_12V_19
12V VCC
B108
VCC_12V_20
12V VCC
B109
VCC_12V_21
12V VCC
B110
GND_27
Power Ground
The termination resistors in this table are already mounted on the module. Refer to the
design guide for information about additional termination resistors.
54
COMe-mTT10 / System Resources
DP-I
PD ~50R(PU @ reset) in
TNC
DP-I
PD ~50R(PU @ reset) in
TNC
I-3.3
PU 10k V3.3V_S0 / PD 100k -
DP-I
PD ~50R(PU @ reset) in
TNC
DP-I
PD ~50R(PU @ reset) in
TNC
I-3.3
PU 1k 3.3V_S5
I-3.3
PU 1k 3.3V_S5
DP-I
PD ~50R(PU @ reset) in
TNC
DP-I
PD ~50R(PU @ reset) in
TNC
PWR
-
DP-O
-
DP-O
-
DP-O
-
DP-O
-
DP-O
-
DP-O
-
DP-I
-
DP-I
-
O-3.3
buffered; forced LOW in
S5/S3
PWR
-
DP-O
100-200MHz
DP-O
100-200MHz
O-3.3
-
PWR
-
PWR
-
PWR
-
PWR
-
I-3.3
PU ~15k in CPLD 3.3V_S5
nc
-
PWR
-
DP-I
100-200MHz
DP-I
100-200MHz
DP-I
-
DP-I
-
nc
optional use by COMe
Type1
nc
optional use by COMe
Type1
O
3.3V_S5
O
-
I/O
-
PWR
-
nc
-
nc
-
nc
-
PWR
-
PWR
-
PWR
-
PWR
-
PWR
-
PWR
-
PWR
-
-
-
-
-
-
-
-
-
-
SDVO
SDVO
SDVO
SDVO
SDVO
SDVO
SDVO
SDVO
-
-
SDVO
SDVO
-
-
-
-
-
For ext.SPI
not supported
-
SDVO
SDVO
SDVO
SDVO
-
-
-
-
-
-
not supported
not supported
-
-
-
-
-
-
-
-
Advertisement
Table of Contents
