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A61
PCIE_TX2+
PCIe lane #2 Transmit+
A62
PCIE_TX2-
PCIe lane #2 Transmit-
A63
SDIO_D1 / GPI1
SDIO#0 Data1 / General Purpose Input 1
A64
PCIE_TX1+
PCIe lane #1 Transmit+
A65
PCIE_TX1-
PCIe lane #1 Transmit-
A66
GND_9
Power Ground
A67
SDIO_D2 / GPI2
SDIO#0 Data2 / General Purpose Input 2
A68
PCIE_TX0+
PCIe lane #0 Transmit+
A69
PCIE_TX0-
PCIe lane #0 Transmit-
A70
GND_10
Power Ground
A71
LVDS_A0+
LVDS Channel A DAT0+
A72
LVDS_A0-
LVDS Channel A DAT0-
A73
LVDS_A1+
LVDS Channel A DAT1+
A74
LVDS_A1-
LVDS Channel A DAT1-
A75
LVDS_A2+
LVDS Channel A DAT2+
A76
LVDS_A2-
LVDS Channel A DAT2-
A77
LVDS_VDD_EN
LVDS Panel Power Control
A78
LVDS_A3+
LVDS Channel A DAT3+
A79
LVDS_A3-
LVDS Channel A DAT3+
A80
GND_11
Power Ground
A81
LVDS_A_CK+
LVDS Channel A Clock+
A82
LVDS_A_CK-
LVDS Channel A Clock-
A83
LVDS_I2C_CK
LVDS I2C Clock (DDC)
A84
LVDS_I2C_DAT
LVDS I2C Data (DDC)
A85
SDIO_D3 / GPI3
SDIO# Data3 / General Purpose Input 3
A86
RSVD
Not Connected
A87
RSVD
Not Connected
A88
PCIE0_CK_REF+
PCIe Clock (positive)
A89
PCIE0_CK_REF-
PCIe Clock (negative)
A90
GND_12
Power Ground
A91
SPI_POWER
Power supply for Carrier Board SPI
A92
SPI_MISO
Data in to Module from Carrier SPI
A93
SDIO_Clk / GPO0
SDIO#0 Clock / General Purpose Output 0
A94
SPI_CLK
Clock from Module to Carrier SPI
A95
SPI_MOSI
Data out from Module to Carrier SPI
A96
TPM_PP
(TPM) Physical Presence pin
A97
TYPE10#
Indicates TYPE10# to carrier board
A98
SER0_TX
UART transmitter
A99
SER0_RX
UART receiver
A100
GND_14
Power Ground
A101
SER1_TX
UART transmitter / optional CAN-TX
A102
SER1_RX
UART receiver / optional CAN-RX
A103
LID#
LID button
A104
VCC_12V_7
12V VCC
A105
VCC_12V_8
12V VCC
A106
VCC_12V_9
12V VCC
A107
VCC_12V_10
12V VCC
A108
VCC_12V_11
12V VCC
A109
VCC_12V_12
12V VCC
A110
GND_15
Power Ground
52
COMe-mTT10 / System Resources
DP-O
PD ~50R(PU @ reset) in
TNC
DP-O
PD ~50R in TNC
I/O-3.3
PU 10k/100k to V3.3_S0
DP-O
PD ~50R(PU @ reset) in
TNC
DP-O
PD ~50R in TNC
PWR
-
I/O-3.3
PU 10k/100k to V3.3_S0
DP-O
PD ~50R(PU @ reset) in
TNC
DP-O
PD ~50R in TNC
PWR
-
DP-O
-
DP-O
-
DP-O
-
DP-O
-
DP-O
-
DP-O
-
O-3.3
buffered; forced LOW in
S5/S3
DP-O
-
DP-O
-
PWR
-
DP-O
-
DP-O
-
IO-3.3
PU 10k 3.3V_S0
IO-3.3
PU 10k 3.3V_S0
I/O-3.3
PU 10k/100k to V3.3_S0
nc
-
nc
-
DP-O
-
DP-O
-
PWR
-
PWR
-
I-3.3
-
O-3.3
- / PD 100k
O-3.3
-
O-3.3
-
I-3.3
PD 4.7k
O
PD 4.7k
O-3.3
-
I-3.3
PU 47k / 10k 3.3V_S0
PWR
-
O-3.3
-
I-3.3
PU 47k / 10k 3.3V_S0
nc
-
PWR
-
PWR
-
PWR
-
PWR
-
PWR
-
PWR
-
PWR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20-80MHz
20-80MHz
-
-
-
-
-
100MHz
100MHz
-
100mA (max.)
-
-
20MHz
-
-
-
14.5V tolerance
14.5V tolerance
-
14.5V / 3.3V tolerance
14.5V / 3.3V tolerance
not supported
-
-
-
-
-
-
-
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