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GOWIN Arora V 138K Programming And Configuration Manual

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Arora Ⅴ 138K FPGA Product
Programming and Configuration
Guide
UG704-1.0.2E, 10/31/2023

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Summary of Contents for GOWIN Arora V 138K

  • Page 1 Arora Ⅴ 138K FPGA Product Programming and Configuration Guide UG704-1.0.2E, 10/31/2023...
  • Page 2 Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is the trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 04/20/2023 1.0E Initial version published. 05/06/2023 1.0.1E The pin “DIN” updated to “MISO” in MSPI mode.  The formula for calculating the loading time of the configuration file fixed. 10/31/2023 1.0.2E  IDCODE and POR Rails for GW5A-138 and GW5AS- 138 added.

  • Page 4: Table Of Contents

    Contents Contents Contents ........................i List of Figures ......................iii List of Tables ......................v 1 About This Guide ....................1 1.1 Purpose ............................1 1.2 Related Documents ........................1 1.3 Terminology and Abbreviations ....................1 1.4 Support and Feedback ....................... 2 2 Glossary ........................
  • Page 5 Contents 3.8 SERIAL ............................ 41 3.8.1 Connection Diagram for SERIAL Configuration Mode............42 3.9 Daisy Chain ..........................43 3.9.1 Serial Daisy Chain ........................ 43 3.9.2 Parallel Daisy Chain ......................44 4 Configuration Details .................... 45 4.1 Configuration Notes ......................... 45 4.2 Configuration Sequence ......................

  • Page 6: List Of Figures

    List of Figures List of Figures Figure 3-1 Configuring Pin Reuse...................... 13 Figure 3-2 Configuration Clock Structure in Master Modes ............... 13 Figure 3-3 Connection Diagram for JTAG Configuration Mode ............14 Figure 3-4 Connection Diagram of JTAG Programming External Flash ..........14 Figure 3-5 JTAG Configuration timing ....................
  • Page 7 List of Figures Figure 3-33 MSPI Configuration Timing ..................... 37 Figure 3-34 The Flow Chart of MSPI Mode ..................38 Figure 3-35 Connection Diagram for CPU Mode ................39 Figure 3-36 CPU Mode Configuration Timing ..................40 Figure 3-37 Continuous Data Loading Timing ................... 41 Figure 3-38 Non Continuous Data Loading Timing ................
  • Page 8 Table 3-5 Pin Reuse Options ......................11 Table 3-6 JTAG Configuration Timing Parameters ................15 Table 3-7 Arora V 138K FPGA IDCODE .................... 18 Table 3-8 Change of TDI and TMS Value in The Process of Sending Instructions ......19 Table 3-9 SSPI Configuration Timing Parameters ................

  • Page 9: About This Guide

    This guide mainly introduces general features and functions on programming and configuration of Arora V FPGA products. It helps users ® to use Gowin FPGA products to their full potential. 1.2 Related Documents The latest user guides are available on the GOWINSEMI website. You can find the related documents at www.gowinsemi.com:...

  • Page 10: Support And Feedback

    FPGA executes after the programming or configuration is complete. 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways.

  • Page 11: Glossary

    Table 2-1 Glossary Glossary Meaning Write the bitstream data generated by Gowin Software to the embedded Program Flash or external SPI Flash of FPGA. Load the bitstream data generated by Gowin software to the FPGA Configure SRAM via external interfaces or embedded Flash.
  • Page 12 After you write the bitstream with security bit to the device Security Bit SRAM, no one will be able to read back the data. Gowin Software sets a security bit for the bitstream data of all FPGA products by default.

  • Page 13: Configuration Interfaces

    3 Configuration Interfaces Configuration Interfaces 3.1 Configuration Modes Arora Ⅴ FPGA products (138K) offer four configuration interfaces. Each configuration interface supports one or more configuration modes and bus widths, as show in Table 3-1. Table 3-1 Configuration Modes Configuration Mode MODE[2:0] Bus Width Description...

  • Page 14: Configuration Pins

    Users can also configure them according to their configuration functions to meet specific requirements. Table 3-2 and Table 3-3 contain a list of all the configuration pins of Gowin FPGA products together with the details of the pins used in each configuration mode and the shared pins in chip packages.

  • Page 15: Table 3-3 Configuration Pin List (2 Of 2)

    3 Configuration Interfaces 3.2 Configuration Pins D[09-15] D[16-31] Note! [1] The pin is located in BANK4 in wirebond package and BANK3 in other packages. Please refer to the related pinout guide for the detailed information. Table 3-3 Configuration Pin List (2 of 2) Master CPU Slave CPU Slave SPI...

  • Page 16: Table 3-4 Pin Definitions

    After FPGA powers up or a low pulse triggers RECONFIG_N, the device enters the corresponding configuration mode in accordance with the MODE value. The same MODE value of the different Gowin series of FPGA products may have different configuration MODE. As the number of pins for each package is different, some...
  • Page 17 3 Configuration Interfaces 3.2 Configuration Pins Pin Name Functional Description If DONE is high, the device has been awakened and enters into the working  state.  If DONE is low, the configuration process is incomplete or fails. As an input configuration pin, the user can delay the wake up process by pulling down the DONE signal externally.
  • Page 18 3 Configuration Interfaces 3.2 Configuration Pins Pin Name Functional Description For CPU master mode, tie to GND directly or via a 1 kΩ (or less) resistor. For CPU slave mode: An external configuration controller can control CSI_B for selecting the active FPGA on the bus, or in a daisy-chain configuration, connect to the CSO_B pin of the upstream FPGA.

  • Page 19: Table 3-5 Pin Reuse Options

    To maximize the utilization of I/O, Gowin FPGA product support for setting the configuration pins as GPIO pins. Before any configuration operation is performed on all series of Gowin FPGA products after power up, all related configuration pins are used as configuration pins by default.
  • Page 20 JTAG command from being triggered by mistake. Pin Reuse Configuration Users can configure pin reuse via Gowin Software. 1. Open the corresponding project in Gowin Software; 2. Select “Project > Configuration > Dual-Purpose Pin” in the menu bar, as shown in Figure 3-1;...

  • Page 21: Configuration Clock For Master Modes

    3 Configuration Interfaces 3.3 Configuration Clock for Master Modes Figure 3-1 Configuring Pin Reuse 3.3 Configuration Clock for Master Modes There are two options for the configuration clock in master modes (master CPU mode, master SERIAL mode, and master SPI mode): On- chip oscillator and external reference clock.

  • Page 22: Jtag Configuration Mode

    IEEE1532 standard and the IEEE1149.1 boundary scan standard. The JTAG configuration mode writes bitstream data to the SRAM of Gowin FPGA products. All configuration data is lost after the device is powered down. All Gowin FPGA products support the JTAG configuration mode.

  • Page 23: Jtag Configuration Timing

    3 Configuration Interfaces 3.4 JTAG Configuration Mode interface. 3.4.2 JTAG Configuration Timing See Figure 3-5 for the timing of JTAG mode. Figure 3-5 JTAG Configuration timing Tj_clk Tclkh Tj_tmshd Tj_tmssu Tj_dsu Tj_dhd Tj_dvld See Table 3-6 for the description of timing parameters. Table 3-6 JTAG Configuration Timing Parameters Name Description...

  • Page 24: Figure 3-6 Tap State Machine

    3 Configuration Interfaces 3.4 JTAG Configuration Mode shown in Figure 3-6. Figure 3-6 TAP State Machine UG704-1.0.2E 16(70)

  • Page 25: Figure 3-7 Instruction Register Access Timing

    3 Configuration Interfaces 3.4 JTAG Configuration Mode TAP Reset After TMS keeps high (logic "1") and at least 5 strobes are input (higher and then low) at the TCK terminal, the TAP logic is reset, the TAP state machine in other states is converted into the state of test logic reset, and the JTAG port and the test logic are reset.

  • Page 26: Figure 3-8 Data Register Access Timing

    ID Code, i.e. JEDEC ID Code, is a basic identification of FPGA products. The length of the Gowin FPGA ID Code is 32 bits. The ID Codes are listed in the table below. Table 3-7 Arora V 138K FPGA IDCODE...

  • Page 27: Figure 3-9 Flow Chart Of Reading Id Code State Machine

    3 Configuration Interfaces 3.4 JTAG Configuration Mode Table 3-8 Change of TDI and TMS Value in The Process of Sending Instructions Value TCK 1 TCK 2 TCK 3 TCK 4 TCK 5 TCK 6 TCK 7 TCK 8 TDI value (0x11) TMS value 4.

  • Page 28: Figure 3-10 Access Timing Of Reading Id Code Instruction-0X11

    Read ID Code. The user code adopts the checksum value in the FS file by default. It can be redefined using Gowin Designer. Reload 0x3C This instruction is used to read the bitstream files from Flash and write to SRAM.
  • Page 29 FPGA functions. SRAM is configured via JTAG to avoid the influence of Configuration Mode Pins. Generate the FS file using Gowin software. Configure SRAM using JTAG. The process of SRAM configuration using the external Host is as follows, as shown in Figure 3-12.

  • Page 30: Figure 3-12 Sram Configuration Flow

    3 Configuration Interfaces 3.4 JTAG Configuration Mode Figure 3-12 SRAM Configuration Flow Start Check ID Code SRAM Erase (Option) Transfer Config Enable Instruction (0x15) Transfer Address Init Instruction (0x12) Transfer Write Instruction (0x17) Transfer Bitstream(MSB) Transfer Config Disable Instruction (0x3A) Transfer NOOP Instruction (0x02)

  • Page 31: Figure 3-13 Process View Of Programming Spi Flash

    3 Configuration Interfaces 3.4 JTAG Configuration Mode ExFlash Programming Program External Flash via JTAG-SPI In this mode, users can simulate Master SPI timing to program SPI Flash via the JTAG interface. TMS corresponds to CS signal, TCK to SCLK signal, TDI to SI signal, and TDO to SO signal. Please refer to the figure below for the flow of programming Flash in this mode.

  • Page 32: Figure 3-14 Timing Diagram Of Jtag-Spi Sending 0X06 (Arora Series)

    3 Configuration Interfaces 3.4 JTAG Configuration Mode Figure 3-14 Timing diagram of JTAG-SPI Sending 0x06 (Arora series) TAP States 0x06(MSB) Run-Test/Idle 1-RUN-Test/IDLE 2-Select-DR-SCAN Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR SVF (Serial Vector Format) Programming External Flash SVF is a syntax specification describing high-level IEEE 1149.1 (JTAG) bus operations.

  • Page 33: Figure 3-16 Otp Configuration Flow

    3 Configuration Interfaces 3.4 JTAG Configuration Mode OTP Configuration Araro Ⅴ series of FPGA products supports one-time programming and provides 128 Bit OTP space. Bit0 ~ Bit31 is the user space, which can be used to store security and other important information. Bit32~Bit95 is the DNA space, which stores the 64-bit unique identification information of the device.

  • Page 34: Figure 3-17 Process Of Reading Otp

    3 Configuration Interfaces 3.4 JTAG Configuration Mode Read OTP The process of reading data is as shown in the figure below. Figure 3-17 Process of reading OTP Start Check ID Read ID Code Code Transfer ISC_Enable Instruction (0x15) Transfer rd_efuse_all_data Instruction (0x2d) Wait 0.036ms Transfer rd_user_data...

  • Page 35: Sspi

    Flash. The MODE value of the Flash programming is the same as that of SSPI configuration mode. Configuration data can be written to SRAM or an external Flash using Gowin programmer. Before loading from the external Flash, the MODE value should be adjusted to MSPI MODE, and UG704-1.0.2E...

  • Page 36: Sspi Configuration Timing

    3 Configuration Interfaces 3.5 SSPI then the MSPI loading can be triggered by powering on again or triggering RECONFIG_N. The connection diagram for programming an external Flash via SSPI is shown in Figure 3-20. Figure 3-20 Connection Diagram of Programming External Flash via SSPI 3.5.2 SSPI Configuration Timing See Figure 3-21 for the SSPI timing.

  • Page 37: Sspi Configuration Instructions

    3 Configuration Interfaces 3.5 SSPI Table 3-9 SSPI Configuration Timing Parameters Name Description Min. Max. Unit Tsspi_clk SSPI port clock period 10.0 – Tsspi_csu sspi_enablen setup time – Tsspi_chd sspi_enablen hold time – Tsspi_dsu SSPI input data setup time – Tsspi_dhd SSPI input data hold time –...

  • Page 38: Figure 3-22 Read Id Code Timing

    3 Configuration Interfaces 3.5 SSPI Read ID Code The length of FPGA ID Code is 32bits. The instruction to read ID is four Bytes, that is 0x11000000. Before sending instructions, keep CS at a high level and generate multiple clocks (more than two) to let FPGA to get CS state.

  • Page 39: Figure 3-25 Write Data (0X3B) Timing

    3 Configuration Interfaces 3.5 SSPI The timing of 0x1500 and 0x3A00 is basically the same. Instructions start at CS low level and the CS is pulled up after the instruction transmission is completed. Instructions following this timing are as follows: 0x3C00 (Reconfig / Reprogram), 0x1500(Write Enable), 0x3A000(Write Disable), 0x1600(Program SPI Flash), 0x1200(Init Address), 0x0500(Erase SRAM).

  • Page 40: Sram Configuration Via Sspi

    3 Configuration Interfaces 3.5 SSPI 3.5.4 SRAM Configuration via SSPI Figure 3-26 The Flow Chart of SRAM Configuration via SSPI Start Read Staus Code Erase SRAM Init Address Write Enable Write Bitstream Data(MSB) Write Disable UG704-1.0.2E 32(70)

  • Page 41: Flash Programming Via Sspi

    3 Configuration Interfaces 3.5 SSPI 3.5.5 Flash Programming via SSPI Figure 3-27 shows the programming flow. First, sends the "Program SPI Flash" (0x1600) instruction to FPGA via SSPI. After this, the FPGA can forward SSPI to Flash, and the SSPI on the Host side can directly access Flash.

  • Page 42: Sram Configuration Via Sspix4

    3 Configuration Interfaces 3.5 SSPI 3.5.6 SRAM Configuration via SSPIx4 The SRAM configuration process via SSPI mode is as follows. The Read Status, Reinit, EraseSram, InitAddress, WriteEnable, and WriteDisble commands are the same with those of SSPI. Only Write Data uses the QSSPI command.

  • Page 43: Mspi

    3.6.1 Connection Diagram for MSPI Configuration Mode The connection diagram for configuring Gowin FPGA products through MSPI is shown in Figure 3-30 ~ Figure 3-32. Figure 3-30 Connection Diagram for MSPIx1 Configuration Mode...

  • Page 44: Figure 3-31 Connection Diagram For Mspix2 Configuration Mode

    3 Configuration Interfaces 3.6 MSPI Figure 3-31 Connection Diagram for MSPIx2 Configuration Mode FPGA SPI Flash CCLK MSCN CS_N MOSI MISO Note! [1] MSPI x2 frequency range: 2.5Mhz~105Mhz  [2] The default configuration is MSPI x1, 3Byte addressing mode, which can be ...

  • Page 45: Mspi Configuration Timing

    3 Configuration Interfaces 3.6 MSPI 3.6.2 MSPI Configuration Timing MSPI configuration timing is as shown in Figure 3-33. Figure 3-33 MSPI Configuration Timing Tmspi_clk Tclkh CCLK FCS_B Tmspi_cvld Tmspi_cvld MOSI (and other output data pins) Tmspi_dvld MISO (and other input data pins) Tmspi_dsu Tmspi_dhd Table 3-11 shows the timing parameters.

  • Page 46: Figure 3-34 The Flow Chart Of Mspi Mode

    3 Configuration Interfaces 3.6 MSPI Figure 3-34 The Flow Chart of MSPI Mode Start First Boot Fail? Second Boot Manu-mode Fail? User-mode Note! [1] The default configuration of the first loading is MSPI x1, 3Byte addressing Read  mode, which can be changed in the EDA software to improve the loading time. [2] The second loading address can be set in the EDA tool.

  • Page 47: Cpu Configuration Mode

    3 Configuration Interfaces 3.7 CPU Configuration Mode 3.7 CPU Configuration Mode The CPU configuration interface supports 8/16/32 bit width, which can adjust the bus width adaptively and supports 8-bit width data readback. Both master mode and slave mode are supported. The only difference between the master mode and the slave mode is the direction of the interface clock.

  • Page 48: Configuration Timing

    3 Configuration Interfaces 3.7 CPU Configuration Mode 3.7.2 Configuration Timing CPU Timing is as shown in Figure 3-36. Figure 3-36 CPU Mode Configuration Timing Tcpu_clk Tclkh CCLK RDWR_B Tcpu_rwsu Tcpu_rwhd CSI_B Tcpu_cssu Tcpu_cshd DATA (as input) Tcpu_dsu Tcpu_dhd CCLK RDWR_B Tcpu_rwsu Tcpu_rwhd CSI_B...

  • Page 49: Continuous Data Loading

    3.8 SERIAL In SERIAL mode, Host configures Gowin FPGA products via serial interface. SERIAL is one of the configuration modes that use the least number of pins. It supports both master mode and slave mode. The only difference between the two modes is the different direction of the interface clock.

  • Page 50: Connection Diagram For Serial Configuration Mode

    3 Configuration Interfaces 3.8 SERIAL 3.8.1 Connection Diagram for SERIAL Configuration Mode The connection diagram for the SERIAL mode is shown in Figure 3-39. Figure 3-39 Connection Diagram for SERIAL Mode Note! [1] CCLK is output in the master mode and input in the slave mode. SERIAL Configuration Timing See Figure 3-40 for the timing of SERIAL mode.

  • Page 51: Daisy Chain

    3 Configuration Interfaces 3.9 Daisy Chain SERIAL port enable  RECONFIG_N is not set as a GPIO during the first configuration after power up or the previous programming. Initiate new configuration  Power-on again or trigger RECONFIG_N at one low pulse. 3.9 Daisy Chain 3.9.1 Serial Daisy Chain In a serial daisy chain, a device receives its configuration data...

  • Page 52: Parallel Daisy Chain

    3 Configuration Interfaces 3.9 Daisy Chain 3.9.2 Parallel Daisy Chain In the parallel Daisy chain, the "chip selection" signal is transmitted from the upstream device to the downstream device. The most upstream device can be in one of the following modes: Master CPU ...

  • Page 53: Configuration Details

    Gowin FPGA products have abundant packages. The configuration modes supported by each device are related to the number of configuration pins bonded out: All devices support JTAG configuration. The mode value for each configuration mode is different.

  • Page 54: Figure 4-2 Power Recycle Timing

    4 Configuration Details 4.1 Configuration Notes Power supply voltage needs to be stable in the process of FPGA start-up. RECONFIG_N needs to keep high after being powered up until the voltage is stable for 1ms and also in the process of FPGA initialization. RECONFIG_N can be vacant or external pulled up.

  • Page 55: Table 4-1 Timing Parameters Of Power On Again And Reconfig_N Triggering For Arora Ⅴ Fpga

    4 Configuration Details 4.1 Configuration Notes Table 4-1 shows the timing parameters of Arora Ⅴ series of FPGA products. Table 4-1 Timing Parameters of Power on Again and RECONFIG_N triggering for Arora Ⅴ FPGA Products Name Description Min. Max. Time from application of V and V to the 23ms...

  • Page 56: Configuration Sequence

    4 Configuration Details 4.2 Configuration Sequence 4.2 Configuration Sequence GOWINSEMI FPGA products will go through initialization, SRAM configuration after power-up. Table 4-5 shows the configuration process. Figure 4-4 GOWINSEMI FPGA Configuration Process Power Up POR Release (VCC/VCCIO/VCCX meets POR requirements) Initialization READY internally driven Low DONE internally driven Low...

  • Page 57: Power-Up Timing

    4 Configuration Details 4.2 Configuration Sequence You can control the timing of the device starting to load by forcing the READY pin  low. You can control the timing of the device waking up by forcing the DONE pin low. ...

  • Page 58: Configuration

    4 Configuration Details 4.2 Configuration Sequence The READY pin has two functions during the initialization phase: Indicates that the FPGA is currently clearing the internal configuration  SRAM. Acts as an input preventing the FPGA from exiting the initialization  state when it’s driven low by an external driver.

  • Page 59: Safety Precautions

    If a CRC error is detected, any data transmitted following this error will be ignored. The "DONE" indicator will not light up after configuration, and the CRC error message will be displayed on the Gowin programmer interface. UG704-1.0.2E...

  • Page 60: Bitstream File Configuration

    GOWINSEMI takes no responsibility for the security of the external Flash. 4.4 Bitstream File Configuration The features of Gowin FPGA products need to be configured and programmed using Gowin software. The settings mainly include the options of configuration pin multiplexing and bitstream data configuration.

  • Page 61: Configure Data Encryption

    Figure 4-6 Configuration Options Note! The security bit setting is forcibly checked after Gowin software verifies the encryption key setting option. In addition to ensuring the data is secure during the transmission process, using these bitstream settings during configuration also prevents any readback, thereby ensuring maximum protection of user data.

  • Page 62: Figure 4-7 Encryption Key Setting Method

    Key. This operation is named as "lock" in this manual. When it's locked, all the read back data is 1. Enter Encryption KEY Refer to the steps below to write the encryption keys in Gowin Software: 1. Open the corresponding project in Gowin Software;...

  • Page 63: Figure 4-8 Setting The Decryption Key

    Note! The initial value of the Gowin FPGA keys is 0. If a key value is changed to 1, it cannot be changed back to 0. For example, the key value written during an operation is 00000000- 00000000-00000000-00000001, and the last bit of the modified key must be 1.

  • Page 64: Figure 4-9 Aes Security Configuration

    4.4 Bitstream File Configuration Programming Operation Gowin Programmer offers the tool for programming AES encryption key. Open this tool by clicking "Edit > Security Key Setting" in Gowin Programmer, as shown in Figure 4-9. Figure 4-9 AES Security Configuration This configuration contains the following three parts: Write: Write Key;...

  • Page 65: Figure 4-10 Prepare

    4 Configuration Details 4.4 Bitstream File Configuration Programming Flow Figure 4-10~ Figure 4-13 shows the flow of how to program or lock the AES key. All the flows are based on JTAG protocol. ID CODE Check the device ID to determine whether the JTAG protocol works properly and whether the programming object is correct to avoid misoperation.

  • Page 66: Figure 4-11 Read Aes Key Flow

    4 Configuration Details 4.4 Bitstream File Configuration Read AES Key Figure 4-11 Read AES Key Flow Transmit ISC Enable Command (0x15) Transmit Read Key Command (0x25) Delay 100 ms Read 128 Bits Transmit ISC Disable Command (0x3A) Stop UG704-1.0.2E 58(70)

  • Page 67: Figure 4-12 Program Aes Key Flow

    4 Configuration Details 4.4 Bitstream File Configuration Program AES Key Figure 4-12 Program AES Key Flow Check ID Read ID Code Code Transfer ISC_Enable Instruction (0x15) Transfer Prgm_key Instruction (0x21) Transfer Key_Data Wait 3.1ms Transfer ISC_disable Instruction (0x3A) UG704-1.0.2E 59(70)

  • Page 68: Figure 4-13 Program Aes Key2 Flow

    4 Configuration Details 4.4 Bitstream File Configuration Figure 4-13 Program AES Key2 Flow Check ID Read ID Code Code Transfer ISC_Enable Instruction (0x15) Transfer Prgm_key2 Instruction (0x29) Transfer Key2_Data Wait 3.1ms Transfer ISC_disable Instruction (0x3A) UG704-1.0.2E 60(70)

  • Page 69: Figure 4-14 Lock Aes Key Flow

    4 Configuration Details 4.4 Bitstream File Configuration Lock AES Key Locking the AES Key prevents the Key leakage. After locking the AES Key, you will not be able to read or configure the AES Key. Figure 4-14 Lock AES Key Flow Transmit ISC Enable Command (0x15) Note!

  • Page 70: Configuration File Size

    4.4 Bitstream File Configuration 4.4.3 Configuration File Size The Gowin bitstream format can be ASCII with annotations or Binary with no annotations. The file with a. fs suffix is a text format file. Lines beginning with “//” are annotations. The others are the bitstream data. The file with a .bin suffix is a binary format file, with no annotations.

  • Page 71: Configuration File Loading Time

    4.4 Bitstream File Configuration 4.4.4 Configuration File Loading Time Gowin FPGA can be used as Master to read bitstream files from Flash and configure SRAM. In Autoboot mode, FPGA reads bitstream files from internal Flash. In MSPI mode, FPGA reads bitstream files from external Flash.

  • Page 72: Spi Flash Selection

    4-byte dual output fast read 8’h3C 4-byte quad output fast read 8’h6C Note! At least one of the Flash read instruction supported by GOWIN FPGAs must be 03 or 0B, and the capacity must be not less than 64Mb. UG704-1.0.2E 64(70)

  • Page 73: Status Register And Efuse Definition

    5 Status Register and Efuse Definition 5.1 Status Register Status Register and Efuse Definition 5.1 Status Register A Status Register is provided inside the device for debugging. By reading the Status Register, the state of the device can be preliminarily determined, such as whether the wakeup is successful, whether there is a loading error, etc.
  • Page 74 5 Status Register and Efuse Definition 5.1 Status Register Device GW5A-138 / GW5AT -138 / GW5AST-138 / GW5AS-138 Status Register[31:0] indicates no security bit is set.) Encrypted Format (1 indicates that the data stream file is encrypted) Encrypted Key Is Right (1 indicates that the Key is right, 0 indicates that the Key is wrong) SSPI_MODE Ser_Crc_Done...

  • Page 75: Otp Efuse

    5 Status Register and Efuse Definition 5.2 OTP Efuse 5.2 OTP Efuse Araro Ⅴ series of FPGA products provide 128 Bit OTP space and support one-time programming and. Bit0 ~ Bit31 is the user space, which can be used to store security and other important information. Bit32~Bit95 is the DNA space, which stores the 64-bit unique identification information of the device.

  • Page 76: Multi Boot And Background Update

    6 Multi Boot and Background Update 6.1 Multi Boot Process Multi Boot and Background Update The multi boot of GOWINSEMI Arora Ⅴ series of FPGA products support flexible dynamic configuration and reliable background upgrade. When an error is detected during configuration, the FPGA can trigger a fallback feature that ensures a Golden firmware can be loaded into the device.

  • Page 77: Figure 6-1 Multi-Configuration Flow

    6 Multi Boot and Background Update 6.1 Multi Boot Process Figure 6-1 Multi-Configuration Flow Power Up Boot MultiBoot Bitstream1 Boot Fail? User Mode1 Reboot? Boot Golden Bitstream Boot MultiBoot Memory Map of Flash Bitstream2 User Mode3 Golden Bitstream Boot Fail? Golden_Address Multiboot Bitstream2 User Mode2...

  • Page 78: Background Upgrade And Hotboot

    JTAG/SSPI/QSSPI or UserLogic. Please refer to 3 Configuration Interfaces for accessing Flash through the JTAG/SSPI/QSSPI interface. For accessing Flash through UserLogic, GOWIN official IP needs to be used. To improve system robustness, it is advised to reserve Golden Bistream area during remote upgrades.

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