User Manuals: ARTERY AT32F423 Series ARM Cortex-M4F MCU

Manuals and User Guides for ARTERY AT32F423 Series ARM Cortex-M4F MCU. We have 2 ARTERY AT32F423 Series ARM Cortex-M4F MCU manuals available for free PDF download: Reference Manual, Getting Started Manual

ARTERY AT32F423 Series Reference Manual (518 pages)

ARM-based 32-bit CortexTM-M4F MCU, 64 to 256 KB Flash, sLib, 15 timers, 1 ADC, 18 communication interfaces (CAN and OTGFS)

Brand: ARTERY | Category: Computer Hardware | Size: 14 MB

Table of Contents
2
AHB Peripheral Clock Enable in Low Power Mode Register
3
System Architecture
34
Figure 1-1 AT32F423 Series Microcontrollers System Architecture
34
System Overview
35
ARM Cortex
35
TM -M4F Processor
35
Bit Band
35
Figure 1-2 Internal Block Diagram of Cortex TM -M4F
35
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a
36
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B
36
Table 1-1 Bit-Band Address Mapping in SRAM
37
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
37
Interrupt and Exception Vectors
38
Table 1-3 AT32F423 Series Vector Table
38
System Tick (Systick)
41
Reset
41
Figure 1-5 Reset Process
41
Figure 1-6 Example of MSP and PC Initialization
42
List of Abbreviations for Registers
43
Device Characteristics Information
43
Flash Memory Size Register
43
Device Electronic Signature
43
Table 1-4 List of Abbreviations for Registers
43
Table 1-5 Base Address and Reset Value of Registers
43
Memory Resources
44
Internal Memory Address Map
44
Flash Memory
44
Figure 2-1 AT32F423 Address Mapping
44
Table 2-1 Flash Memory Organization (256 KB)
45
Table 2-2 Flash Memory Organization (128 KB)
45
Table 2-3 Flash Memory Organization (64 KB)
45
SRAM Memory
46
Peripheral Address Map
46
Table 2-4 Peripheral Boundary Address
46
Power Control (PWC)
49
Introduction
49
Main Features
49
Por/Lvr
49
Figure 3-1 Block Diagram of each Power Supply
49
Power Voltage Monitor (PVM)
50
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
50
Figure 3-3 PVM Threshold and Output
50
Power Domain
51
Power Saving Modes
51
PWC Registers
53
Power Control Register (PWC_CTRL)
53
Table 3-1 PWC Register Map and Reset Values
53
Power Control/Status Register (PWC_CTRLSTS)
54
LDO Output Voltage Select Register (PWC_LDOOV)
55
Clock and Reset Manage (CRM)
56
Clock
56
Clock Sources
56
Figure 4-1 AT32F423 Clock Tree
56
System Clock
58
Peripheral Clock
58
Clock Fail Detector
58
Auto Step-By-Step System Clock Switch
58
Internal Clock Output
58
Interrupts
59
Reset
59
System Reset
59
Battery Powered Domain Reset
59
Figure 4-2 System Reset Circuit
59
CRM Registers
60
Clock Control Register (CRM_CTRL)
60
Table 4-1 CRM Register Map and Reset Values
60
PLL Clock Configuration Register (CRM_PLLCFG)
61
Clock Configuration Register (CRM_CFG)
62
Clock Interrupt Register (CRM_CLKINT)
64
AHB Peripheral Reset Register 1 (CRM_AHBRST1)
65
AHB Peripheral Reset Register 2 (CRM_AHBRST2)
65
AHB Peripheral Reset Register 3 (CRM_AHBRST3)
66
APB1 Peripheral Reset Register (CRM_APB1RST)
66
APB2 Peripheral Reset Register (CRM_APB2RST)
67
AHB Peripheral Clock Enable Register 1 (CRM_AHBEN1)
68
AHB Peripheral Clock Enable Register 2 (CRM_AHBEN2)
68
AHB Peripheral Clock Enable Register 3 (CRM_AHBEN3)
69
APB1 Peripheral Clock Enable Register (CRM_APB1EN)
69
APB2 Peripheral Clock Enable Register (CRM_APB2EN)
70
AHB Peripheral Clock Enable in Low Power Mode Register
71
(Crm_Ahblpen1)
71
(Crm_Ahblpen2)
72
(Crm_Ahblpen3)
72
APB1 Peripheral Clock Enable in Low Power Mode Register (CRM_APB1LPEN)
72
APB2 Peripheral Clock Enable in Low Power Mode Register (CRM_APB2LPEN)
73
Peripheral Independent Clock Select Register (CRM_PICLKS)
74
Battery Powered Domain Control Register (CRM_BPDC)
74
Control/Status Register (CRM_CTRLSTS)
75
Additional Register 1 (CRM_MISC1)
76
Additional Register 2 (CRM_MISC2)
77
Flash Memory Controller (FLASH)
78
FLASH Introduction
78
Table 5-1 Flash Memory Architecture (256 K)
78
Table 5-2 Flash Memory Architecture (128 K)
78
Table 5-3 Flash Memory Architecture (64 K)
78
Table 5-4 User System Data Area
79
Flash Memory Operation
80
Unlock/Lock
80
Erase Operation
80
Figure 5-1 Flash Memory Sector Erase Process
81
Programming Operation
82
Figure 5-2 Flash Memory Mass Erase Process
82
Figure 5-3 Flash Memory Programming Process
83
Read Operation
84
Main Flash Memory Extension Area
84
User System Data Area Operation
84
Unlock/Lock
84
Erase Operation
84
Programming Operation
85
Figure 5-4 System Data Area Erase Process
85
Read Operation
86
Flash Memory Protection
86
Figure 5-5 System Data Area Programming Process
86
Access Protection
87
Erase/Program Protection
87
Table 5-5 Flash Memory Access Limit
87
Read Access
88
Special Functions
88
Security Library Settings
88
Boot Memory Used as Flash Memory Extension
89
CRC Verify
89
FLASH Memory Registers
89
Table 5-6 Flash Memory Register Map and Reset Value
89
Flash Performance Select Register (FLASH_PSR)
90
Flash Unlock Register (FLASH_UNLOCK)
91
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
91
Flash Status Register (FLASH_STS)
91
Flash Control Register (FLASH_CTRL)
91
Flash Address Register (FLASH_ADDR)
92
User System Data Register (FLASH_USD)
92
Erase/Program Protection Status Register (FLASH_EPPS)
92
Flash Security Library Status Register 0 (SL IB_STS0)
93
Flash Security Library Status Register 1 (SLIB_STS1)
93
Security Library Password Clear Register (SLIB_PWD_CLR)
94
Security Library Additional Status Register (SLIB_MISC_STS)
94
Flash CRC Address Register (FLASH_CRC_ADDR)
94
Flash CRC Control Register (FLASH_CRC_CTRL)
94
Flash CRC Check Result Register (FLASH_CRC_CHKR)
95
Security Library Password Setting Register (SLIB_SET_PWD)
95
Security Library Address Se Tting Register (SLIB_SET_RANGE)
95
Flash Extension Memory Security Library Setting Register
96
(Em_Slib_Set)
96
Boot Memory Mode Setting Register (BTM_MODE_SET)
96
Security Library Unlock Register (SLIB_UNLOCK)
96
Gpios and IOMUX
97
Introduction
97
Function Overview
97
GPIO Structure
97
Figure 5-6 GPIO Basic Structure
97
GPIO Reset Status
98
General-Purpose Input Configuration
98
Analog Input/Output Configuration
98
General-Purpose Output Configuration
98
I/O Port Protection
99
IOMUX Structure
99
Figure 5-7 IOMXU Structure
99
Multiplexed Function Pull-Up/Down Configuration
100
IOMUX Input/Output
100
Table 5-7 Port a Multiplexed Function Configuration with GPIOA_MUX* Register
100
Table 5-8 Port B Multiplexed Function Configuration with GPIOA_MUX* Register
102
Table 5-9 Port C Multiplexed Function Configuration with GPIOA_MUX* Register
104
Table 5-10 Port D Multiplexed Function Configuration with GPIOA_MUX* Register
106
Table 5-11 Port E Multiplexed Function Configuration with GPIOA_MUX* Register
108
Peripheral MUX Function Configuration
110
IOMUX Mapping Priority
110
Table 5-12 Port F Multiplexed Function Configuration with GPIOA_MUX* Register
110
Table 5-13 Pins Owned by Hardware
110
External Interrupt/Wake-Up Lines
111
GPIO Registers
111
Table 5-14 GPIO Register Map and Reset Values
111
GPIO Configuration Register (Gpiox_Cfgr) (X=A
112
GPIO Output Mode Register (Gpiox_Omode) (X=A
112
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A
112
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A
112
GPIO Input Data Register (Gpiox_Idt) (X=A
112
GPIO Output Data Register (Gpiox_Odt) (X=A
113
GPIO Set/Clear Register (Gpiox_Scr) (X=A
113
GPIO Write Protection Register (Gpiox_Wpr) (X=A
113
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A
113
GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A
114
GPIO Port Bit Clear Register (Gpiox_Clr) (X=A
114
GPIO Port Bit Toggle Register (Gpiox_Togr) (X=A
114
GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A
114
System Configuration Controller (SCFG)
115
Introduction
115
SCFG Registers
115
SCFG Configuration Register 1 (SCFG_CFG1)
115
SCFG Configuration Register 2 (SCFG_CFG2)
115
Table 7-1 SCFG Register Map and Reset Value
115
SCFG External Interrupt Configuration Register 3 (SCFG_EXINTC3)
117
SCFG Ultra High Souring/Sinking Strength (SCFG_UHDRV)
119
External Interrupt/Event Controller (EXINT)
120
EXINT Introduction
120
Function Overview and Configuration Procedure
120
Figure 8-1 External Interrupt/Event Controller Block Diagram
120
EXINT Registers
121
Interrupt Enable Register (EXINT_INTEN)
121
Event Enable Register (EXINT_EVTEN)
121
Polarity Configuration Register 1 (EXINT_POLCFG1)
121
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
121
Polarity Configuration Register 2 (EXINT_POLCFG2)
122
Software Trigger Register (EXINT_SWTRG)
122
Interrupt Status Register (EXINT_INTSTS)
122
DMA Controller (DMA)
123
Introduction
123
Main Features
123
Function Overview
123
DMA Configuration
123
Figure 9-1 DMA Block Diagram
123
Handshake Mechanism
124
Arbiter
124
Programmable Data Transfer Width
124
Figure 9-2 Re-Arbitrate after Request/Acknowledge
124
Errors
125
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
125
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
125
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
125
Table 9-1 DMA Error Event
125
Interrupts
126
DMA Multiplexer (DMAMUX)
126
DMAMUX Function Overview
126
Figure 9-6 DMAMUX Block Diagram
126
Table 9-2 DMA Interrupts
126
Table 9-3 Flexible DMA1 / DMA2 Request Mapping
127
DMAMUX Overflow Interrupts
128
Figure 9-7 DMAMUX Request Synchronized Mode
128
Table 9-4 DMAMUX EXINT LINE for Trigger Input and Synchronized Input
128
DMA Registers
129
Figure 9-8 DMAMUX Event Generation
129
Table 9-5 DMA Register Map and Reset Value
129
DMA Interrupt Status Register (DMA_STS )
130
DMA Interrupt Flag Clear Register (DMA_CLR)
132
DMA Channel-X Configuration Register (Dma_Cxctrl) (X = 1
134
DMA Channel-X Number of Data Register (Dma_Cxdtcnt
134
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr)
135
DMA Channel-X Memory Address Register (Dma_Cxmaddr
135
DMAMUX Select Register (DMA_MUXSEL)
135
DMAMUX Channel-X Control Register (Dma_Muxcxctrl
135
DMAMUX Generator-X Control Register (Dma_Muxgxctrl
136
DMAMUX Channel Synchronization Status Register (DMA_MUXSYNCSTS)
136
DMAMUX Channel Interrupt Clear Register (DMA_MUXSYNCCLR)
137
DMAMUX Generator Interrupt Status Register (DMA_MUXGSTS)
137
DMAMUX Generator Interrupt Clear Register (DMA_MUXGCLR)
137
CRC Calculation Unit (CRC)
138
CRC Introduction
138
CRC Function Overview
138
Figure 10-1 CRC Block Diagram
138
CRC Registers
139
Data Register (CRC_DT)
139
Common Data Register (CRC_CDT)
139
Table 10-1 CRC Register Map and Reset Value
139
Control Register (CRC_CTRL)
140
Initialization Register (CRC_IDT)
140
C Interface
141
I 2 C Instruction
141
I 2 C Main Features
141
C Function Overview
141
Figure 11-1 I C Bus Protocol
141
I 2 C Interface
142
Figure 11-2 I 2 C1 Interface Block Diagram
142
Figure 11-3 Block Diagram of I
142
C Timing Control
144
Figure 11-4 Setup and Hold Time
144
Data Transfer Management
146
Table 11-1 I 2 C Timing Specifications
146
I 2 C Master Communication Flow
147
Table 11-2 I 2 C Configuration Table
147
Figure 11-5 I 2 C Master Transmission Flow
149
Figure 11-6 Transfer Sequence of I
150
Figure 11-7 I 2 C Master Receive Flow
150
Figure 11-8 Transfer Sequence of I
151
Figure 11-9 10-Bit Address Read Access When READH10=1
151
I 2 C Slave Communication Flow
152
Figure 11-10 10-Bit Address Read Access When READH10=0
152
Figure 11-11 I 2 C Slave Transmission Flow
154
Figure 11-12 I 2 C Slave Transmission Timing
154
Figure 11-13 I 2 C Slave Receive Flow
155
Figure 11-14 I C Slave Receive Timing
155
Smbus
156
Table 11-3 Smbus Timeout Specification
157
Table 11-4 Smbus Timeout Detection Configuration
157
Smbus Master Communication Flow
158
Table 11-5 Smbus Mode Configuration
158
Figure 11-15 Smbus Master Transmission Flow
159
Figure 11-16 Smbus Master Transmission Timing
160
Figure 11-17 Smbus Master Receive Flow
160
Smbus Slave Communication Flow
161
Figure 11-18 Smbus Master Receive Timing
161
Figure 11-19 Smbus Slave Transmission Flow
163
Figure 11-20 Smbus Slave Transmission Timing
164
Figure 11-21 Smbus Slave Transmission Timing
164
Data Transfer Using DMA
165
Figure 11-22 Smbus Slave Receive Timing
165
Error Management
166
Table 11-6 I 2 C Error Event
166
Wakeup from Deepsleep Mode at Address Matching Event
167
I 2 C Interrupt Requests
167
Table 11-7 I 2 C Interrupt Requests
167
I 2 C Debug Mode
168
I 2 C Registers
168
Control Register 1 (I2C_CTRL1)
168
Table 11-8 I 2 C Register Map and Reset Values
168
Control Register 2 (I2C_CTRL2)
169
Own Address Register 1 (I2C_OADDR1)
170
Own Address Register 2 (I2C_OADDR2)
170
Timing Register (I2C_CLKCTRL)
170
Timeout Register (I2C_TIMEOUT)
171
Status Register (I2C_STS)
171
Status Clear Register (I2C_CLR)
172
PEC Register (I2C_PEC)
173
Receive Data Register (I2C_RXDT)
173
Transmit Data Register (I2C_TXDT)
173
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
174
USART Introduction
174
Figure 12-1 USART Block Diagram
174
Full-Duplex/Half-Duplex Selector
175
Mode Selector
176
Introduction
176
Configuration Procedure
176
Figure 12-2 BFF and FERR Detection in LIN Mode
176
Figure 12-3 Smartcard Frame Format
177
Figure 12-4 Irda DATA(3/16) - Normal Mode
177
Figure 12-5 Hardware Flow Control
178
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection
178
USART Frame Format and Configuration
179
Figure 12-7 8-Bit Format USART Synchronous Mode
179
Figure 12-8 Word Length Configuration
180
DMA Transfer Introduction
181
Transmission Using DMA
181
Figure 12-9 Stop Bit Configuration
181
Reception Using DMA
182
Baud Rate Generation
182
Introduction
182
Configuration
182
Table 12-1 Error Calculation for Programmed Baud Rate
182
Transmitter
183
Transmitter Introduction
183
Transmitter Configuration
183
Figure 12-10 Variations When Transmitting TDC/TDBE
183
Receiver
184
Receiver Introduction
184
Receiver Configuration
184
Start Bit and Noise Detection
185
Table 12-2 Data Sampling over Start Bit and Noise Detection
185
Table 12-3 Data Sampling over Valid Data and Noise Detection
185
Low-Power Wakeup
186
Tx/Rx Swap
186
Figure 12-11 Data Sampling for Noise Detection
186
Interrupt Requests
187
Figure 12-12 Tx/Rx Swap
187
Figure 12-13 USART Interrupt Map Diagram
187
Table 12-4 USART Interrupt Requests
187
I/O Pin Control
188
USART Registers
188
Status Register (USART_STS)
188
Table 12-5 USART Register Map and Reset Value
188
Data Register (USART_DT)
190
Baud Rate Register (USART_BAUDR)
190
Control Register 1 (USART_CTRL1)
190
Control Register 2 (USART_CTRL2)
192
Control Register 3 (USART_CTRL3)
193
Guard Time and Divider Register (GDIV)
194
Receiver Timeout Detection Register (RTOV)
194
Interrupt Flag Clear Register (IFC)
194
Serial Peripheral Interface (SPI)
195
SPI Introduction
195
Functional Overview
195
SPI Description
195
Figure 13-1 SPI Block Diagram
195
Full-Duplex/Half-Duplex Selector
196
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
196
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
197
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
197
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
197
Chip Select Controller
198
SPI_SCK Controller
198
Crc
199
DMA Transfer
200
TI Mode
200
Transmitter
201
Receiver
201
Motorola Mode
202
Figure 13-6 Master Full-Duplex Communications
202
Figure 13-7 Slave Full-Duplex Communications
203
Figure 13-8 Master Half-Duplex Transmit
203
Figure 13-9 Slave Half-Duplex Receive
203
TI Mode
204
Figure 13-10 Slave Half-Duplex Transmit
204
Figure 13-11 Master Half-Duplex Receive
204
Figure 13-12 TI Mode Continous Transfer
204
Interrupts
205
IO Pin Control
205
Precautions
205
Figure 13-13 TI Mode Continous Transfer with Dummy CLK
205
Figure 13-14 TI Mode Continous Transfer with Dummy CLK
205
Figure 13-15 SPI Interrupts
205
I 2 S Functional Description
206
I S Introduction
206
Figure 13-16 I 2 S Block Diagram
206
I S Full-Duplex
207
Operating Mode Selection
207
Figure 13-17 I S Full-Duplex Structure
207
Figure 13-18 I 2 S Slave Device Transmission
208
Figure 13-19 I 2 S Slave Device Reception
208
Figure 13-20 I 2 S Master Device Transmission
208
Audio Protocol Selector
209
Figure 13-21 I S Master Device Reception
209
I2S_CLK Controller
210
Figure 13-22 CK & MCK Source in Master Mode
210
DMA Transfer
211
Table 13-1 Audio Frequency Precision Using System Clock
211
Transmitter/Receiver
212
Interrupts
213
IO Pin Control
213
SPI Registers
213
SPI Control Register1 (SPI_CTRL1)
213
Mode)
213
Figure 13-23 I S Interrupts
213
Table 13-2 SPI Register Map and Reset Value
213
SPI Control Register2 (SPI_CTRL2)
215
SPI Status Register (SPI_STS)
215
SPI Data Register (SPI_DT)
216
SPICRC Register (SPI_CPOLY)
216
Mode)
216
Spirxcrc Register (SPI_RCRC)
216
Spitxcrc Register (SPI_TCRC)
217
SPI_I2S Register (SPI_I2SCTRL)
217
SPI_I2S Prescaler Register (SPI_I2SCLKP)
218
Timer
219
Table 14-1 TMR Functional Comparison
219
Basic Timer (TMR6 and TMR7)
220
TMR6 and TMR7 Introduction
220
TMR6 and TMR7 Main Features
220
TMR6 and TMR7 Function Overview
220
Counting Clock
220
Counting Mode
220
Figure 14-1 Basic Timer Block Diagram
220
Figure 14-2 Control Circuit with CK_INT Divided by 1
220
Debug Mode
221
Figure 14-3 Basic Structure of a Counter
221
Figure 14-4 Overflow Event When PRBEN=0
221
Figure 14-6 Counting Timing Diagram When the Prescaler Division Is 4
221
TMR6 and TMR7 Registers
222
TMR6 and TMR7 Control Register1 (Tmrx_Ctrl1)
222
Table 14-2 TMR6 and TMR7 Register Table and Reset Value
222
TMR6 and TMR7 Control Register2 (Tmrx_Ctrl2)
223
TMR6 and TMR7 Dma/Interrupt Enable Register (Tmrx_Iden)
223
TMR6 and TMR7 Interrupt Status Register (Tmrx_Ists)
223
TMR6 and TMR7 Software Event Register (Tmrx_Sw EVT)
223
TMR6 and TMR7 Counter Value (Tmrx_Cval)
223
TMR6 and TMR7 Division (Tmrx_Div)
223
TMR6 and TMR7 Period Register (Tmrx_Pr)
224
General-Purpose Timer (TMR2 to TMR4)
225
TMR2 to TMR4 Introduction
225
TMR2 to TMR4 Main Features
225
TMR2 to TMR4 Functional Overview
225
Counting Clock
225
Figure 14-7 General-Purpose Timer Block Diagram
225
Figure 14-8 Counting Clock
225
Figure 14-9 Control Circuit with CK_INT, Tmrx_Div=0X0 and Tmrx_Pr=0X16
226
Figure 14-10 Block Diagram of External Clock Mode a
227
Figure 14-11 Counting in External Clock Mode A, Pr=0X32 and DIV=0X0
227
Figure 14-12 Block Diagram of External Clock Mode B
227
Figure 14-13 Counting in External Clock Mode B, Pr=0X32 and DIV=0X0
227
Counting Mode
228
Figure 14-14 Counter Timing with Prescaler Value Chang from 1 to 4
228
Table 14-3 Tmrx Internal Trigger Connection
228
Figure 14-5 Overflow Event When PRBEN=1
229
Figure 14-15 Basic Structure of a Counter
229
Figure 14-16 Overflow Event When PRBEN=0
229
Figure 14-17 Overflow Event When PRBEN=1
229
Figure 14-18 Counter Timing Diagram with Internal Clock Divided by 4
229
Figure 14-19 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
230
Figure 14-20 Encoder Mode Structure
230
Figure 14-21 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
231
Table 14-4 Counting Direction Versus Encoder Signals
231
TMR Input Function
232
Figure 14-22 Input/Output Channel 1 Main Circuit
232
Figure 14-23 Channel 1 Input Stage
232
Figure 14-24 PWM Input Mode Configuration Example
233
Figure 14-25 PWM Input Mode
233
TMR Output Function
234
Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 to 4)
235
Figure 14-27 C1ORAW Toggles When Counter Value Matches the C1DT Value
236
Figure 14-28 Upcounting Mode and PWM Mode a
236
Figure 14-29 Up/Down Counting Mode and PWM Mode a
237
Figure 14-30 One-Pulse Mode
237
TMR Synchronization
238
Figure 14-31 Clearing Cxoraw(PWM Mode A) by EXT Input
238
Figure 14-32 Example of Reset Mode
238
Figure 14-33 Example of Suspend Mode
238
Figure 14-34 Example of Trigger Mode
239
Figure 14-35 Master/Slave Timer Connection
239
Debug Mode
240
TMR2 to TMR4 Registers
240
Figure 14-36 Using Master Timer to Start Slave Timer
240
Figure 14-37 Starting Master and Slave Timers Synchronously by an External Trigger
240
Control Register 1 (Tmrx_Ctrl1)
241
Table 14-5 TMR2 to TMR4 Register Map and Reset Value
241
Control Register 2 (Tmrx_Ctrl2)
242
Slave Timer Control Register (Tmrx_Stctrl)
242
Dma/Interrupt Enable Register (Tmrx_Iden)
243
Interrupt Status Register (Tmrx_Ists)
244
Software Event Register (Tmrx_Sw EVT)
245
Channel Mode Register1 (Tmrx_Cm1)
245
Channel Mode Register2 (Tmrx_Cm2)
247
Channel Control Register (Tmrx_Cctrl)
248
Counter Value (Tmrx_Cval)
249
Frequency Division Value (Tmrx_Div)
249
Period Register (Tmrx_Pr)
249
Channel 1 Data Register (Tmrx_C1Dt)
249
Table 14-6 Standard Cxout Channel Output Control Bit
249
Channel 2 Data Register (Tmrx_C2Dt)
251
Channel 3 Data Register (Tmrx_C3Dt)
251
Channel 4 Data Register (Tmrx_C4Dt)
251
DMA Control Register (Tmrx_Dmactrl)
251
DMA Data Register (Tmrx_Dmadt)
252
General-Purpose Timer (TMR9 and TMR12)
252
TMR9 and TMR12 Introduction
252
TMR9 and TMR12 Main Features
252
TMR9 and TMR12 Functional Overview
252
Counting Clock
252
Figure 14-38 Block Diagram of General-Purpose TMR9/12
252
Figure 14-39 Counting Clock
253
Figure 14-40 Control Circuit with CK_INT, Tmrx_Div=0X0 and Tmrx_Pr=0X16
253
Figure 14-41 Block Diagram of External Clock Mode a
254
Figure 14-42 Counting in External Clock Mode A, Pr=0X32 and DIV=0X0
254
Table 14-7 Tmrx Internal Trigger Connection
254
Counting Mode
255
Figure 14-43 Counter Timing with Prescaler Value Chang from 1 to 4
255
Figure 14-44 Basic Structure of a Counter
255
Figure 14-45 Overflow Event When PRBEN=0
256
Figure 14-46 Overflow Event When PRBEN=1
256
Figure 14-47 Counter Timing Diagram with Internal Clock Divided by 4
256
Figure 14-48 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
257
Figure 14-49 OVFIF in Upcounting Mode and Central-Aligned Mode
258
Figure 14-50 Encoder Mode Structure
259
Table 14-8 Counting Direction Versus Encoder Signals
259
TMR Input Function
260
Figure 14-51 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
260
Figure 14-52 Input/Output Channel 1 Main Circuit
260
Figure 14-53 Channel 1 Input Stage
261
Figure 14-54 PWM Input Mode Configuration Example
262
Figure 14-55 PWM Input Mode
262
TMR Output Function
263
Figure 14-56 Channel 1 Output Stage
263
Figure 14-57 Channel 2 Output Stage
263
Figure 14-58 C1ORAW Toggles When Counter Value Matches the C1DT Value
264
Figure 14-59 Upcounting Mode and PWM Mode a
264
Figure 14-60 One-Pulse Mode
265
TMR Break Function
266
Figure 14-61 Complementary Output with Dead-Time Insertion
266
TMR Synchronization
267
Figure 14-62 TMR Output Control
267
Figure 14-63 Example of TMR Break Function
267
Debug Mode
268
Figure 14-64 Example of Reset Mode
268
Figure 14-65 Example of Suspend Mode
268
Figure 14-66 Example of Trigger Mode
268
TMR9 and TMR12 Registers
269
TMR9 and TMR12 Control Register1 (Tmrx_Ctrl1)
269
Table 14-9 TMR9 and TMR12 Register Map and Reset Value
269
TMR9 and TMR12 Control Register 2 (Tmrx_Ctrl2)
270
TMR9 and TMR12 Slave Timer Control Register (TMR1_STCTRL)
271
TMR9 and TMR12 Dma/Interrupt Enable Register (Tmrx_Iden)
271
TMR9 and TMR12 Interrupt Status Register (Tmrx_Ists)
272
TMR9 and TMR12 Software Event Register (Tmrx_Swevt)
273
TMR9 and TMR12 Channel Mode Register 1 (Tmrx_Cm1)
273
TMR9 and TMR12 Channel Control Register (Tmrx_Cctrl)
275
TMR9 and TMR12 Counter Value (Tmrx_Cval)
276
TMR9 and TMR12 Division Value (Tmrx_Div)
276
TMR9 and TMR12 Period Register (Tmrx_Pr)
276
TMR9 and TMR12 Repetition Period Register (Tmrx_Rpr)
276
TMR9 and TMR12 Channel 1 Data Register (Tmrx_C1Dt)
276
TMR9 and TMR12 Channel 2 Data Register (Tmrx_C2Dt)
277
TMR9 and TMR12 Break Register (Tmrx_Brk)
277
TMR9 and TMR12 DMA Control Register (Tmrx_Dmactrl)
278
TMR9 and TMR12 DMA Data Register (Tmrx_Dmadt)
278
General-Purpose Timer (TMR10/11/13/14)
279
Tmrx Introduction
279
Tmrx Main Features
279
Tmrx Functional Overview
279
Counting Clock
279
Figure 14-67 TMR10/11/13/14 Block Diagram
279
Figure 14-68 Basic Structure of a Counter
279
Counting Mode
280
Figure 14-69 Control Circuit with CK_INT, Tmrx_Div=0X0 and Pr=0X16
280
Figure 14-70 Basic Structure of a Counter
280
Figure 14-71 Overflow Event When PRBEN=0
281
Figure 14-72 Overflow Event When PRBEN=1
281
Figure 14-73 Counter Timing Diagram with Internal Clock Divided by 4
281
Figure 14-74 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
282
TMR Input Function
283
Figure 14-75 OVFIF in Upcounting Mode and Central-Aligned Mode
283
TMR Output Function
284
Figure 14-76 Input/Output Channel 1 Main Circuit
284
Figure 14-77 Channel 1 Input Stage
284
Figure 14-78 Channel 1 Output Stage
284
Figure 14-79 C1ORAW Toggles When Counter Value Matches the C1DT Value
286
Figure 14-80 Upcounting Mode and PWM Mode a
286
Figure 14-81 One-Pulse Mode
286
TMR Break Function
287
Figure 14-82 Complementary Output with Dead-Time Insertion
287
Debug Mode
288
Figure 14-83 TMR Output Control
288
Figure 14-84 Example of TMR Break Function
288
Tmrx Registers
289
Tmrx Control Register1 (Tmrx_Ctrl1) (X=10/11/13/14)
289
Table 14-10 TMR10/11/13/14 Register Map and Reset Value
289
Tmrx Control Register 2 (Tmrx_Ctrl2) (X=10/11/13/14)
290
Tmrx Dma/Interrupt en Able Register (Tmrx_Iden
290
Tmrx Interrupt Status Register (Tmrx_Ists) (X=10/11/13/14)
291
Tmrx Software Event Register (Tmrx_Swevt) (X=10/11/13/14)
291
Tmrx Channel Mode Register1 (Tmrx_Cm1) (X=10/11/13/14)
292
Tmrx Channel Control Register (Tmrx_Cctrl) (X=10/11/13/14)
293
Table 14-11 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
294
Tmrx Counter Value (Tmrx_Cval) (X=10/11/13/14)
295
Tmrx Division Value (Tmrx_Div) (X=10/11/13/14)
295
Tmrx Period Register (Tmrx_Pr) (X=10/11/13/14)
295
Tmrx Repetition Period Register (Tmrx_Rpr) (X=10/11/13/14)
295
Tmrx Channel 1 Data Register (Tmrx_C1Dt) (X=10/11/13/14)
295
Tmrx Break Register (Tmrx_Brk) (X=10/11/13/14)
295
TMRX DMA Control Register (TMRX_DMACTRL) (X=10/11/13/14)
297
Tmrx DMA Data Register (Tmrx_Dmadt) (X=10/11/13/14)
297
TMR14 Channel Input Remap Register (Tmrx_Rmp)
297
Advanced-Control Timers (TMR1)
298
TMR1 Introduction
298
TMR1 Main Features
298
TMR1 Functional Overview
298
Counting Clock
298
Figure 14-85 Block Diagram of Advanced-Control Timer
298
Figure 14-86 Counting Clock
299
Figure 14-87 Control Circuit with CK_INT, Tmrx_Div=0X0 and Tmrx_Pr=0X16
299
Figure 14-88 Block Diagram of External Clock Mode a
300
Figure 14-89 Counting in External Clock Mode A, Pr=0X32 and DIV=0X0
300
Figure 14-90 Block Diagram of External Clock Mode B
300
Counting Mode
301
Figure 14-91 Counting in External Clock Mode B, Pr=0X32 and DIV=0X0
301
Figure 14-92 Counter Timing with Prescaler Value Changing from 1 to 4
301
Table 14-12 Tmrx Internal Trigger Connection
301
Figure 14-93 Basic Structure of a Counter
302
Figure 14-94 Overflow Event When PRBEN=0
302
Figure 14-95 Overflow Event When PRBEN=1
302
Figure 14-96 Counter Timing Diagram with Internal Clock Divided by 4
303
Figure 14-97 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
303
Figure 14-98 OVFIF Behavior in Upcounting Mode and Center-Aligned Mode
304
Figure 14-99 Structure of Encoder Mode
304
Figure 14-100 Example of Encoder Interface Mode C
305
Table 14-13 Counting Direction Versus Encoder Signals
305
TMR Input Function
307
Figure 14-101 Input/Output Channel 1 Main Circuit
307
Figure 14-102 Channel 1 Input Stage
307
Figure 14-103 PWM Input Mode Configuration Example
308
TMR Output Function
309
Figure 14-104 PWM Input Mode
309
Figure 14-105 Channel Output Stage (Channel 1 to 3)
309
Figure 14-106 Channel 4 Output Stage
309
Figure 14-107 C1ORAW Toggles When Counter Value Matches the C1DT Value
311
Figure 14-108 Upcounting Mode and PWM Mode a
311
Figure 14-109 Up/Down Counting Mode and PWM Mode
311
Figure 14-110 One-Pulse Mode
312
Figure 14-111 Clearing Cxoraw (PWM Mode A) by EXT Input
312
TMR Break Function
313
Figure 14-112 Complementary Output with Dead-Time Insertion
313
TMR Synchronization
314
Figure 14-113 TMR Output Control
314
Figure 14-114 Example of TMR Break Function
314
Figure 14-115 Example of Reset Mode
315
Figure 14-116 Example of Suspend Mode
315
Figure 14-117 Example of Trigger Mode
315
Debug Mode
316
TMR1 Registers
316
TMR1 Control Register1 (TMR1_CTRL1)
316
Table 14-14 TMR1 Register Map and Reset Value
316
TMR1 Control Register2 (TMR1_CTRL2)
317
TMR1 Slave Timer Control Register (TMR1_STCTRL)
318
TMR1 Dma/Interrupt Enable Register (TMR1_IDEN)
319
TMR1 Interrupt Status Register (TMR1_ISTS)
320
TMR1 Software Event Register (TMR1_SWEVT)
321
TMR1 Channel Mode Register1 (TMR1_CM1)
321
TMR1 Channel Mode Register2 (TMR1_CM2)
323
TMR1 Channel Control Register (TMR1_CCTRL)
324
Table 14-15 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
325
TMR1 Counter Value (TMR1_CVAL)
326
TMR1 Division Value (TMR1_DIV)
326
TMR1 Period Register (TMR1_PR)
326
TMR1 Repetition Period Register (TMR1_RPR)
326
TMR1 Channel 1 Data Register (TMR1_C1DT)
326
TMR1 Channel 2 Data Register (TMR1_C2DT)
326
TMR1 Channel 3 Data Register (TMR1_C3DT)
328
TMR1 Channel 4 Data Register (Tmrx_C4Dt)
328
TMR1 Break Register (TMR1_BRK)
328
TMR1 DMA Control Register (TMR1_DMACTRL)
329
TMR1 DMA Data Register (TMR1_DMADT)
330
TMR1 Channel Mode Register3 (TMR1_ CM3)
330
TMR1 Channel 5 Data Register (TMR1_C5DT)
330
Window Watchdog Timer (WWDT)
331
WWDT Introduction
331
WWDT Main Features
331
WWDT Functional Overview
331
Figure 15-1 Window Watchdog Block Diagram
331
Debug Mode
332
WWDT Registers
332
Control Register (WWDT_CTRL)
332
Figure 15-2 Window Watchdog Timing Diagram
332
Table 15-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz
332
Table 15-2 WWDT Register Map and Reset Value
332
Configuration Register (WWDT_CFG)
333
Status Register (WWDT_STS)
333
Watchdog Timer (WDT)
334
WDT Introduction
334
WDT Main Features
334
WDT Functional Overview
334
Debug Mode
335
WDT Registers
335
Figure 16-1 WDT Block Diagram
335
Table 16-1 WDT Timeout Period (Lick=40Khz)
335
Table 16-2 WDT Register and Reset Value
335
Command Register (WDT_CMD)
336
Divider Register (WDT_DIV)
336
Reload Register (WDT_RLD)
336
Status Register (WDT_STS)
336
Window Register (WDT_WIN)
337
Enhanced Real-Time Clock (ERTC)
338
ERTC Introduction
338
ERTC Main Features
338
Figure 17-1 ERTC Block Diagram
338
ERTC Function Overview
339
ERTC Clock
339
ERTC Initialization
339
Table 17-1 RTC Register Map and Reset Values
339
Periodic Automatic Wakeup
341
ERTC Calibration
341
Reference Clock Detection
342
Time Stamp Function
342
Tamper Detection
343
Multiplexed Function Output
343
ERTC Wakeup
344
Table 17-2 ERTC Low-Power Mode Wakeup
344
Table 17-3 Interrupt Control Bits
344
ERTC Registers
345
ERTC Time Register (ERTC_TIME)
345
Table 17-4 ERTC Register Map and Reset Values
345
ERTC Date Register (ERTC_DATE)
346
ERTC Control Register (ERTC_CTRL)
346
ERTC Initialization and Status Register (ERTC_STS)
347
ERTC Divider Register (ERTC_DIV)
349
ERTC Wakeup Timer Register (ERTC_WAT)
349
ERTC Alarm Clock a Register (ERTC_ALA)
349
ERTC Alarm Clock B Register (ERTC_ALB)
349
ERTC Write Protection Register (ERTC_WP)
350
ERTC Subsecond Register (ERTC_SBS)
350
ERTC Time Adjustment Register (ERTC_TADJ)
350
ERTC Time Stamp Time Register (ERTC_TSTM)
350
ERTC Time Stamp Date Register (ERTC_TSDT)
351
ERTC Time Stamp Subsecond Register (ERTC_TSSBS)
351
ERTC Smooth Calibration Register (ERTC_SCAL)
351
ERTC Tamper Configuration Register (ERTC_TAMP)
352
ERTC Alarm Clock a Subsecond Register (ERTC_ALASBS)
353
ERTC Alarm Clock B Subsecond Register (ERTC_ALBSBS)
353
ERTC Battery Powered Domain Data Register (Ertc_Bprx)
353
Analog-To-Digital Converter (ADC)
354
ADC Introduction
354
ADC Main Features
354
ADC Structure
355
Figure 18-1 ADC1 Block Diagram
355
ADC Functional Overview
356
Channel Management
356
Internal Temperature Sensor
356
Internal Reference Voltage
356
ADC Operation Process
356
Power-On and Calibration
357
Figure 18-2 ADC Basic Operation Process
357
Trigger
358
Sampling and Conversion Sequence
358
Figure 18-3 ADC Power-On and Calibration
358
Table 18-1 Trigger Sources for Ordinary and Preempted Channels
358
Conversion Sequence Management
359
Sequence Mode
359
Preempted Group Automatic Conversion Mode
359
Figure 18-4 Sequence Mode
359
Figure 18-5 Preempted Group Auto Conversion Mode
359
Repetition Mode
360
Partition Mode
360
Figure 18-6 Repetition Mode
360
Figure 18-7 Partition Mode
360
End of Conversion
361
Oversampling
361
Figure 18-8 ADABRT Timing Diagram
361
Table 18-2 Correlation between Maximum Cumulative Data, Oversampling Multiple and Shift Digits
361
Oversampling of Ordinary Group of Channels
362
Figure 18-9 Rdinary Oversampling Restart Mode Selection
362
Oversampling of Preempted Group of Channels
363
Data Management
363
Data Alignment
363
Figure 18-10 Ordinary Oversampling Trigger Mode
363
Figure 18-11 Oversampling of Preempted Group of Channels
363
Data Read
364
Voltage Monitoring
364
Figure 18-12 Data Alignment
364
Status Flag and Interrupts
365
ADC Registers
365
Table 18-3 ADC Register Map and Reset Values
365
ADC Status Register (ADC_STS)
366
ADC Control Register1 (ADC_CTRL1)
366
ADC Control Register2 (ADC_CTRL2)
368
ADC Sampling Time Register 1 (ADC_SPT1)
369
ADC Sampling Time Register 2 (ADC_SPT2)
371
ADC Preempted Channel Data Offset Registe R X
373
(ADC_ Pcdtox) (X=1
373
ADC Voltage Monitoring High Threshold Register (ADC_VWHB)
373
ADC Voltage Monitor Low Threshold Register (ADC_ VWLB)
373
ADC Ordinary Sequence Register 1 (ADC_ OSQ1)
373
ADC Ordinary Sequence Register 2 (ADC_ OSQ2)
373
ADC Ordinary Sequence Register 3 (ADC_ OSQ3)
374
ADC Preempted Sequence Register (ADC_PSQ)
374
ADC Preempted Data Register X (ADC_ Pdtx) (X=1
374
ADC Ordinary Data Register (ADC_ ODT)
374
ADC Sampling Time Register 3 (ADC_SPT3)
375
ADC Ordinary Sequence Register 4 (ADC_OSQ4)
376
ADC Ordinary Sequence Register 5 (ADC_OSQ5)
376
ADC Ordinary Sequence Register 6 (ADC_OSQ6)
377
ADC Oversampling Register (ADC_OVSP)
377
ADC Calibration Value Register (ADC_CALVAL)
378
ADC Common Control Register (ADC_CCTRL)
378
Digital-To-Analog Converter (DAC)
379
DAC Introduction
379
DAC Main Features
379
Design Hints and Tips
379
Figure 19-1 DAC1/DAC2 Block Diagram
379
Functional Overview
380
Trigger Events
380
Noise/Triangular-Wave Generation
380
Table 19-1 Trigger Source Selection
380
Figure 19-2 LFSR Register Calculation Algorithm
381
Figure 19-3 Triangular-Wave Generation
381
DAC Data Alignment
382
DAC Registers
382
DAC Control Register (DAC_CTRL)
382
Table 19-2 DAC Register Map and Reset Values
382
DAC Software Trigger Register (DAC_SWTRG)
385
DAC1 12-Bit Right-Aligned Data Holding Register (DAC_D1DTH12R)
385
DAC1 12-Bit Left-Aligned Data Holding Register (DAC_D1DTH12L)
385
DAC1 8-Bit Right-Aligned Data Holding Register (DAC
385
DAC2 12-Bit Right-Aligned Data Holding Register (DAC_D2DTH12R)
385
DAC2 12-Bit Left-Aligned Data Holding Register (DAC_D2DTH12L)
385
DAC2 8-Bit Right-Aligned Data Holding Register (DAC_D2DTH8R)
386
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DDTH12R)386
386
DAC1 Data Output Register (DAC_D1ODT)
386
DAC2 Data Output Register (DAC_D2ODT)
386
DAC Status Register (DAC_STS)
386
Controller Area Network (CAN)
387
CAN Introduction
387

ARTERY AT32F423 Series Getting Started Manual (26 pages)

Brand: ARTERY | Category: Computer Hardware | Size: 1 MB

Table of Contents
2
Development Resources
5
Set up AT32 Development Environment
5
Debug Tools and Evaluation Board
5
Figure 1. AT-START-F423 and AT-Link-EZ
5
Figure 2. AT-START-F423 Evaluation Board Package from ARTERY Official Website
5
Programming Tools and Software Resources
6
AT32 Development Environment
6
Figure 3. ICP/ISP/AT-Link-Family Package from ARTERY Official Website
6
Figure 4. BSP Resources from ARTERY Official Website
6
Figure 5. Keil_V5 Template
7
Figure 6. Pack Resources from ARTERY Official Website
8
Figure 7. Install Arterytek.at32F423_Dfp
8
Figure 8. Install Keil4_At32Mcu_Addon
8
Figure 9. Click "Pack Installer" Icon in Keil
9
Figure 10. Install Iar_At32Mcu_Addon
9
Figure 11. Keil Debug Option
10
Figure 12. Settings Option in Keil Debug
10
Figure 13. Keil Utilities Option
10
Figure 14. IAR Debug Option
11
Figure 15. IAR CMSIS-DAP Option
11
How to Quickly Replace AT32F415 with AT32F423
12
AT32F423 Functionality Enhancement
12
Instruction Prefetch Buffer
12
Figure 16. Wait State Bit in FLASH_PSR Register
12
Figure 17. System_Clock_Config Function
12
PLL Clock Settings
13
Figure 18. AT32F423 150Mhz Output Clock Configuration
13
Figure 19. AT32 PLL Auto Step-By-Step Frequency Switch Configuration Example
13
Encryption
14
Figure 20. Use ISP Tool to Enable or Disable Access Protection
14
Figure 21. Use ISP to Enable Access Protection
15
Figure 22. Use ISP to Unlock Access Protection
15
Figure 23. Use ICP Tool to Enable Erase/Write Protection
16
Set System Memory as Main Memory Extension
17
Figure 24. Use ICP Tool to Disable Erase/Write Protection
17
Figure 25. Use ICP Tool to Set Boot Memory AP Mode
18
Figure 26. Boot Memory AP Mode Operating Progress
18
Figure 27. Use ICP Tool to Set Offline Boot Mode AP Mode
19
Figure 28. Use ICP Tool to Set Offline Project Programming
20
Figure 29. ICP Tool to Monitor Offline Download Status
20
How to Distinguish AT32 MCU from Other Mcus
21
Figure 30. Read Cortex ID
21
Figure 31. Read UID,PID
21
Frequently-Asked Questions for Download and Compiling
22
Program Enters Hard Fault Handler
22
Jlink Unable to Recognize IC in Keil Project
22
Possible Questions Occurred During Download
22
Flash Download Failed-"Cortex-M4
22
Figure 32. Flash Download Failed-"Cortex- M4" During Download
22

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ARTERY AT32F423 Series Reference Manual (518 pages)

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ARTERY AT32F423 Series Getting Started Manual (26 pages)

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