Xilinx Spartan-3A Schematic page 11

DESIGN NOTE: The Revision C board has an inductor in this
location. Shorting across this location improves high-frequency
0Ω
DDR2 SDRAM interface performance.
The Revision D board uses a 0Ω resistor.
0Ω
DESIGN NOTE: The Revision C board has an inductor in this
location. Shorting across this location improves high-frequency
DDR2 SDRAM interface performance.
The Revision D board uses a 0Ω resistor.
32Mx16 DDR2 SDRAM
DDR2 SDRAM device
Termination network
The DDR2 SDRAM interface has specific pin assignment
and layout requirements to support the Xilinx Memory
Interface Generator (MIG) software. See the "DDR SDRAM"
chapter in UG334: Spartan-3A/3AN Starter Kit User
Spartan-3A/3AN Starter Kit Board
32Mx16 DDR2 SDRAM
Connects to FPGA
I/O Bank 3
Guide.
TM