Mitsubishi MELSEC AJ65BT-R2 User Manual page 94

5 PRELIMINARY INFORMATION
Programmable controller CPU
Refer to control data (a)
Refer to interlock signal (b)
Reception data size
Reception data 1
Read data
Reception data n
Reception normal read
request signal
Reception error read
request signal
Reception read complete
signal
(5) When using the RIRCV command
This is used to read a R2-designated buffer memory with executing handshake
automatically between the master station and R2.
When the RIRCV command is used, the master station buffer memory is used for
the control data size transmission buffer, and the master station buffer memory is
used for the read data size reception buffer.
(Example) Reading the reception data
Address
Q/QnA Series A Series
M 1200
Bank 1
H
M 1201
Bank 1
H
M 1202
Bank 1
H
M 1203
Bank 1
H
M 13FF
Bank 1
H
RIRCV command
execution
(RXn2)
(RXn3)
(RYn2)
Master module
(Transmission buffer)
Address
M 1000 to 11FF
H
of Q/QnA Series
R2
0 to 1FF
H
of A Series bank 1
(Reception buffer)
Complete status
+
M 200
H
Station No., request code
+
M 201
H
+
No. of read data (byte)
M 202
H
+
M 203
H
Read data
+
M 3FF
H
At reception
normal completion
At reception
error completion
Reading of buffer
memory
5 - 36
H
H
Address
Reception data size
R2 400
H
designation area
R2 401
H
Reception data storage
area
R2
401+n
H
RIRCV command
execution completion
MELSEC-A
R2