Ad9912 System Clock Pll Loop Filter - Analog Devices AD9912 Quick Start Manual

AD9912 SYSTEM CLOCK PLL LOOP FILTER

The AD9912 system clock PLL has an external loop filter whose
components are tailored for different applications.
If the system clock PLL is bypassed, the LOOPFILTER pin
should be pulled down to ground with a 1 kΩ resistor.
The loop bandwidth of the SYSCLK multiplier PLL can be
adjusted by means of three external components, as shown in
Table 1. The nominal gain of the VCO is 800 MHz/V. The
recommended component values and their locations on the
evaluation board are shown in Table 1. They establish a loop
bandwidth of approximately 1.6 MHz with the charge pump
current set to 250 μA. The default case is N = 40 and assumes a
25 MHz SYSCLK input frequency and generates an internal
DAC sampling frequency (f
S
When modeling the AD9912 system clock PLL, bear in mind
that there is approximately 5 pF of parallel capacitance internal
to Shunt C (C88). The values in Table 1 are the actual values
) of 1 GHz.
that should be used on the board and do not include this
internal capacitance.
The AD9912 features a bipolar edge detector that doubles the
rate of the clock going into the system clock PLL. The
multiplication factors in Table 1 are for the system clock PLL
only. Refer to the AD9912 data sheet for more details on the
system clock PLL and bipolar edge detector.
Table 1. Recommended SYSCLK PLL Loop Filter Values
SYSCLK
Multiplier
8 (or less)
10
20
40 (default)
60
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AD9912/PCBZ
Series R Series C
(R98) (C83)
390 Ω 1 nF
470 Ω 820 pF
1 kΩ 390 pF
2.2 kΩ 180 pF
2.7 kΩ 120 pF
Shunt C
(C88)
82 pF
56 pF
27 pF
10 pF
5 pF