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FEATURES
1 GSPS internal clock speed (up to 400 MHz output directly)
Integrated 1 GSPS 14-bit DAC
48-bit frequency tuning word with 4 µHz resolution
Differential HSTL comparator
Flexible system clock input accepts either crystal or external
reference clock
On-chip low noise PLL REFCLK multiplier
2 SpurKiller channels
Low jitter clock doubler for frequencies up to 750 MHz
Single-ended CMOS comparator; frequencies of <150 MHz
Programmable output divider for CMOS output
Serial I/O control
Excellent dynamic performance
Software controlled power-down
Available in two 64-lead LFCSP packages
Residual phase noise @ 250 MHz
10 Hz offset: −113 dBc/Hz
1 kHz offset: −133 dBc/Hz
100 kHz offset: −153 dBc/Hz
40 MHz offset: −161 dBc/Hz
INTERFACE
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
BASIC BLOCK DIAGRAM
AD9912
STARTUP
S1 TO S4
CONFIGURATION
LOGIC
DIGITAL
SERIAL PORT,
I/O LOGIC
Synthesizer with 14-Bit DAC
APPLICATIONS
Agile LO frequency synthesis
Low jitter, fine tune clock generation
Test and measurement equipment
Wireless base stations and controllers
Secure communications
Fast frequency hopping
GENERAL DESCRIPTION
The AD9912 is a direct digital synthesizer (DDS) that features
an integrated 14-bit digital-to-analog converter (DAC). The
AD9912 features a 48-bit frequency tuning word (FTW) that
can synthesize frequencies in step sizes no larger than 4 μHz.
Absolute frequency accuracy can be achieved by adjusting the
DAC system clock.
The AD9912 also features an integrated system clock phase-
locked loop (PLL) that allows for system clock inputs as low
as 25 MHz.
The AD9912 operates over an industrial temperature range,
spanning −40°C to +85°C.
DAC_OUT
DIRECT
FDBK_IN
DIGITAL
SYNTHESIS
CORE
CLOCK
OUTPUT
DRIVERS
SYSTEM CLOCK
MULTIPLIER
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2007–2009 Analog Devices, Inc. All rights reserved.
1 GSPS Direct Digital
AD9912
FILTER
OUT
OUT_CMOS
www.analog.com
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Table of Contents
Related Manuals for Analog Devices AD9912
Summary of Contents for Analog Devices AD9912
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Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. -
Page 2: Table Of Contents
AD9912 TABLE OF CONTENTS Features ... 1 Applications ... 1 General Description ... 1 Basic Block Diagram ... 1 Revision History ... 2 Specifications ... 3 DC Specifications ... 3 AC Specifications ... 5 Absolute Maximum Ratings ... 7 Thermal Resistance ... 7 ESD Caution ... -
Page 3: Specifications
DVDD_I/O DVSS kΩ mV p-p Rev. D | Page 3 of 40 AD9912 Test Conditions/Comments Pin 37 is typically 3.3 V but can be set to 1.8 V See also the Total Power Dissipation specifications CMOS output driver at 3.3 V, 50 MHz, with... - Page 4 AD9912 Parameter SYSTEM CLOCK INPUT SYSCLK PLL Bypassed Input Capacitance Input Resistance Internally Generated DC Bias Voltage Differential Input Voltage Swing SYSCLK PLL Enabled Input Capacitance Input Resistance Internally Generated DC Bias Voltage Differential Input Voltage Swing Crystal Resonator with SYSCLK PLL Enabled...
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Page 5: Ac Specifications
See Figure 29 for maximum toggle rate; the S-divider should be used for low frequencies because the FDBK_IN minimum frequency is 10 MHz With 20 pF load and up to 150 MHz With 20 pF load AD9912... -
Page 6: Changes To Serial Port Timing Specifications And Propagation Delay Parameters
AD9912 Parameter CMOS Output Driver (AVDD3/Pin 37) @ 1.8 V Frequency Range Duty Cycle Rise Time/Fall Time (20% to 80%) DAC OUTPUT CHARACTERISTICS DCO Frequency Range (1 Nyquist Zone) Output Resistance Output Capacitance Full-Scale Output Current Gain Error Output Offset... -
Page 7: Absolute Maximum Ratings
Note that the exposed pad on the bottom of package must be soldered to ground to achieve the specified thermal performance. See the Typical Performance Characteristics section for more information. ESD CAUTION Rev. D | Page 7 of 40 AD9912 θ θ Unit 13.9 °C/W typical... -
Page 8: Pin Configuration And Function Descriptions
AD9912 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD_I/O DVSS DVDD DVSS DVDD DVSS DVDD DVSS AVDD AVDD3 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Table 5. Pin Function Descriptions Input/ Pin No. - Page 9 50 kΩ pull-down resistor. Chip Select. Active low. When programming a device, this pin must be held low. In systems where more than one AD9912 is present, this pin enables individual programming of each AD9912. This pin has an internal 100 k Ω...
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Page 10: Typical Performance Characteristics
AD9912 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, AVDD3, and DVDD at nominal supply voltage; DAC R phase noise used for generating these plots. –50 –55 –60 –65 –70 –75 –80 OUTPUT FREQUENCY (MHz) Figure 3. Wideband SFDR vs. Output Frequency at −40°C, +25°C, and +85°C, SYSCLK = 1 GHz (SYSCLK PLL Bypassed) –50... - Page 11 Figure 13. Absolute Phase Noise Using HSTL Driver, Generator at 83.33 MHz ) RMS JITTER (12kHz TO 20MHz): 99MHz: 1.41ps 399MHz: 1.46ps 100k FREQUENCY OFFSET (Hz) Figure 14. Absolute Phase Noise Using HSTL Driver, Generator at 25 MHz ) AD9912 100M 399MHz 99MHz 100M 399MHz 99MHz 100M...
- Page 12 AD9912 –100 RMS JITTER (100Hz TO 100MHz): 600MHz: 585fs 800MHz: 406fs –110 –120 800MHz –130 600MHz –140 –150 100k FREQUENCY OFFSET (Hz) Figure 15. Absolute Phase Noise Using HSTL Driver, SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed), HSTL Output Doubler Enabled –110...
- Page 13 FREQUENCY OFFSET (Hz) RMS JITTER (100Hz TO 100MHz): 82fs 100k FREQUENCY OFFSET (Hz) RMS JITTER (100Hz TO 100MHz): 22fs 100k FREQUENCY OFFSET (Hz) LNOM 100-5 Multiplier, LNDD 500-14 Diode Doubler AD9912 100M = 258.3 MHz, 100M = 311.6 MHz, 100M...
- Page 14 AD9912 NOM SKEW 25°C, 1.8V SUPPLY WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY) FREQUENCY (MHz) Figure 27. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs. Toggle Rate (100 Ω Across Differential Pair) NOM SKEW 25°C, 1.8V SUPPLY (20pF) WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY (20pF))
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Page 15: Input/Output Termination Recommendations
INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.01µF AD9912 DOWNSTREAM 1.8V 100Ω HSTL OUTPUT 0.01µF Figure 33. AC-Coupled HSTL Output Driver 50Ω AD9912 DOWNSTREAM 1.8V HSTL AVDD/2 OUTPUT 50Ω Figure 34. DC-Coupled HSTL Output Driver 10pF* AD9912 SELF-BIASING SYSCLK INPUT (CRYSTAL 10pF* MODE) REFER TO CRYSTAL DATA SHEET. -
Page 16: Theory Of Operation
LOGIC S1 TO S4 OVERVIEW The AD9912 is a high performance, low noise, 14-bit DDS clock synthesizer with integrated comparators for applications desiring an agile, finely tuned square or sinusoidal output signal. A digitally controlled oscillator (DCO) is implemented using a direct digital synthesizer (DDS) with an integrated output DAC, clocked by the system clock. -
Page 17: Digital-To-Analog (Dac) Output
= 19.44 MHz, then DAC_OUT RECONSTRUCTION FILTER The origin of the output clock signal produced by the AD9912 is the combined DDS and DAC. The DAC output signal appears as a sinusoid sampled at f determined by the frequency tuning word (FTW) that appears at the input to the DDS. -
Page 18: Fdbk_In Inputs
FDBK_IN INPUTS The FDBK_IN pins serve as the input to the comparators and output drivers of the AD9912. Typically, these pins are used to receive the signal generated by the DDS after it has been band- /2). It also contains limited by the external reconstruction filter. -
Page 19: Sysclk Inputs
SYSCLK INPUTS Functional Description An external time base connects to the AD9912 at the SYSCLK pins to generate the internal high frequency system clock (f The SYSCLK inputs can be operated in one of the following three modes: • SYSCLK PLL bypassed •... - Page 20 AD9912 SYSCLK PLL Multiplier When the SYSCLK PLL multiplier path is employed, the frequency applied to the SYSCLK input pins must be limited so as not to exceed the maximum input frequency of the SYSCLK PLL phase detector. A block diagram of the SYSCLK generator appears in Figure 45.
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Page 21: Output Clock Drivers And 2× Frequency Multiplier
AC Specifications section for the exact frequency limits. 2× Frequency Multiplier The AD9912 can be configured (via the I/O register map) with an internal 2× delay-locked loop (DLL) multiplier at the input of the primary clock driver. The extra octave of frequency gain allows the AD9912 to provide output clock frequencies that exceed the range available from the DDS alone. -
Page 22: Changes To Figure 48
AD9912 Although the worst spurs tend to be harmonic in origin, the fact that the DAC is part of a sampled system results in the possibility of spurs appearing in the output spectrum that are not harmoni- cally related to the fundamental. For example, if the DAC is sampled at 1 GHz and generates an output sinusoid of 170 MHz, the fifth harmonic would normally be at 850 MHz. -
Page 23: Thermal Performance
Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 Ψ Junction-to-top-of-package characterization parameter, 0 m/sec air flow per JEDEC JESD51-2 (still air) The AD9912 is specified for a case temperature (T ensure that T is not exceeded, an airflow source can be used. -
Page 24: Power-Up
AD9912 POWER-UP POWER-ON RESET On initial power-up, the AD9912 internally generates a 75 ns RESET pulse. The pulse is initiated when both of the following two conditions are met: • The 3.3 V supply is greater than 2.35 V ± 0.1 V. -
Page 25: Changes To Power Supply Partitioning Section
POWER SUPPLY PARTITIONING The AD9912 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. The numbers quoted here are for comparison only. Refer to the Specifications section for exact numbers. -
Page 26: Change To Serial Control Port Section
If the instruction word is for a write operation (I15 = 0), the second part is the transfer of data into the serial control port buffer of the AD9912. The length of the transfer (1, 2, or 3 bytes, or streaming mode) is indicated by two bits ([W1:W0]) in the instruction byte. -
Page 27: The Instruction Word (16 Bits)
The AD9912 instruction word and byte data can be MSB first or LSB first. The default for the AD9912 is MSB first. The LSB first mode can be enabled by writing a 1 to the LSB first bit in the serial configuration register and then issuing an I/O update. -
Page 28: Changes To Figure 52
AD9912 Table 10. Serial Control Port, 16-Bit Instruction Word, MSB First SCLK DON'T CARE SDIO DON'T CARE A11 A10 A9 A8 16-BIT INSTRUCTION HEADER Figure 51. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data SCLK DON'T CARE SDIO... - Page 29 Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state HIGH BIT N + 1 Figure 56. Serial Control Port Timing—Write Rev. D | Page 29 of 40 AD9912...
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Page 30: I/O Register Map
AD9912 I/O REGISTER MAP All address and bit locations that are left blank in Table 12 are unused. Table 12. Addr (Hex) Type Name Bit 7 Serial port configuration and part identification 0x0000 Serial config. active 0x0001 Reserved 0x0002 Part ID... - Page 31 × 2 Spur A magnitude, Bits[7:0] Spur A phase, Bits[7:0] Amplitude gain × 2 Spur B magnitude, Bits[7:0] Spur B phase, Bits[7:0] Rev. D | Page 31 of 40 AD9912 Default Bit 2 Bit 1 Bit 0 (Hex) 0x00 0xFF...
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Page 32: I/O Register Descriptions
Resets register map, except for Register 0x0000. Setting this bit forces a soft reset, meaning that S1 to S4 are not tristated, nor is their state read when this bit is cleared. The AD9912 assumes the values of S1 to S4 that were present during the last hard reset. This bit is not self-clearing, and all other registers are restored to their default values after a soft reset. -
Page 33: System Clock (Register 0X0020 To Register 0X0022)
VCO auto range (Bit 7) to set the correct VCO range automatically. [1:0] Charge pump current Charge pump current. 00 = 250 μA. 01 = 375 μA. 10 = off. 11= 125 μA. Rev. D | Page 33 of 40 AD9912... -
Page 34: Cmos Output Divider (S-Divider) (Register 0X0100 To Register 0X0106)
These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity. - Page 35 These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
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Page 36: Doubler And Output Drivers (Register 0X0200 To Register 0X0201)
AD9912 DOUBLER AND OUTPUT DRIVERS (REGISTER 0x0200 TO REGISTER 0x0201) Register 0x0200—HSTL Driver Table 32. Bits Bit Name Description OPOL Output polarity. Setting this bit inverts the HSTL driver output polarity. [3:2] Reserved Reserved. [1:0] HSTL output doubler HSTL output doubler. - Page 37 Spur B Harmonic 1 to Spur B Harmonic 15. Allows user to choose which harmonic to eliminate. Description Linear multiplier for Spur B magnitude. Description Linear offset for Spur B phase. Description Linear offset for Spur B phase. Rev. D | Page 37 of 40 AD9912...
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Page 38: Added Exposed Paddle Notation To Outline Dimensions
AD9912 OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 9.00 0.60 MAX 0.60 MAX 8.75 BSC SQ VIEW 0.50 0.40 0.30 0.80 MAX 0.65 TYP... -
Page 39: Changes To Ordering Guide
−40°C to +85°C AD9912BCPZ-REEL7 −40°C to +85°C AD9912A/PCBZ 1, 2 AD9912/PCBZ Z = RoHS Compliant Part. Recommended for use in new designs; reference PCN 09-0156. Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]... - Page 40 AD9912 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06763-0-11/09(D) Rev. D | Page 40 of 40...
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