Power Supply; Digital Power Supply; Analog Power Supply - Espressif Systems ESP32-C3FH4 Hardware Design Manuallines

2 Schematic Checklist

2.1 Power Supply

For details of using power supply pins, please refer to Section Power Scheme in
ESP32-C3 Family

2.1.1 Digital Power Supply

Pin 11 and pin 17 are the power supply pins for RTC IO and CPU IO respectively, in a voltage range of 3.0 V
GND
3.6 V. We recommend adding 0.1 µF capacitors close to each digital power supply pin.
When working as an output power supply pin, VDD_SPI can be powered by VDD3P3_CPU via R
V). Therefore, there will be a voltage drop on VDD_SPI to VDD3P3_CPU. We recommend adding a 1 µF filter
capacitor between VDD_SPI and ground.
When not working as a power supply pin, VDD_SPI can be used as GPIO11.
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
XTAL_32K_P
5
XTAL_32K_N
6
GPIO2
7
CHIP_EN
8
GPIO3
U2
Notice:
When VDD_SPI works as the power supply pin for embedded and external 3.3 V flash, VDD3P3_CPU should
be 3.0 V or above, so as to fall into flash's operating voltage range.

2.1.2 Analog Power Supply

Pin 2, pin 3, pin 31, and pin 32 are the analog power supply pins, working at 3.0 V
ESP32-C3 family works in transmission (TX) mode, the instantaneous current is higher and may cause a power
rail collapse. Therefore, it is highly recommended to add a 10 µF capacitor to the power trace, which can work in
conjunction with the 0.1 µF capacitor. In addition, a LC filter circuit needs to be added near pin 2 and pin 3 to
suppress high-frequency harmonics. The inductor's rated current is preferably 500 mA or above. Refer to Figure
4
3 and place the appropriate decoupling capacitor near each analog power pin.
Espressif Systems
TBD
GND
40MHz(±10ppm)
Datasheet.
VDD_SPI
VDD3P3_CPU
ESP32-C3
Figure 2: ESP32­C3 Family Digital Power Supply Pins
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TBD
R2
24
R3
SPIQ
23
R4
SPID
22 R5
SPICLK
21
SPICS0
20
R6
SPIWP
19
R7
SPIHD
18
17
C10
0.1uF
GND
C12
0.1uF
GND
3
6
499 U0TXD
U0RXD
GPIO19
GPIO18
0 SPIQ
SPID
0
0 SPICLK
SPICS0
0 SPIWP
0 SPIHD
VDD_SPI
C11
VDD33
1uF
GND
VDD33
~ 3.6 V. Please note that when
ESP32-C3 Family Hardware Design Guidelines V1.0
~
(nominal 3.3
SP I
R8
10K
1
SPICS0
/CS
SPICLK 6
CLK
SPIHD 7
/HOLD
U3
2
VDD
G