Parallel Ata - DIGITAL-LOGIC SmartCore Express SMA200 Technical User's Manual

DIGITAL-LOGIC AG
5.4.5.

Parallel ATA

Signal BUS
PATA_D[15..0] CMOS
PATA_A[0..2] CMOS
PATA_IOR#] CMOS
PATA_IOW#] CMOS
PATA_DACK#] CMOS
PATA_CS[3,1] CMOS
PATA_REQ CMOS
PATA_IORDY CMOS
PATA_IRQ CMOS
PATA_PCSEL CMOS
If the signals are not used:
All this PATA signals may be left open.
Remarks:
EMV/EMI filters:
Are not needed.
Type Description
5V IDE data signals
I/O
5V IDE address signal.
Out Connect directly to the PATA
device.
5V IDE control signal.
Out Connect directly to the
PATA-device.
5V IDE control signal.
Out Connect directly to the
PATA-device.
5V IDE control signal.
Out Connect directly to the
PATA-device.
5V IDE control signal.
Out Connect directly to the
PATA-device.
3/5V IDE control signal.
In Connect directly to the
PATA-device.
3V IDE control signal.
In Connect directly to the
PATA-device.
3V IDE control signal.
In Connect directly to the
PATA-device.
3V GND = SSD works as master
In HIGH = SSD works as slave
On Module Ext. Ter-
Terminatio mination
n Needed
Series 33
-
-
-
-
-
-
PU 4.7k to
3.3V
PU 10k to
3.3V
PD 4.7k to
GND
29
SMA200 Manual V1.0
Max.
Length Ohm
in mm
- 100 55
- 100 55
- 100 55
- 100 55
- 100 55
- 100 55
- 100 55
- 100 55
- 100 55
100 55
Matched
Length
in mm
-