Silicon Laboratories C8051T60x-DK User Manual page 8

C8051T60x-DK
7.4. PORT I/O Connector (J8)
Each of the C8051T60x's I/O pins, as well as VPP, +3VD, GND, and /RST are routed to header J8. This header can
be used to easily connect to any signal on the device. Table 2 defines the pins for header J8.
7.5. Serial Interface (J2)
A RS232 transceiver circuit and DB-9 (J2) connector are provided on the main board to facilitate serial connections
to UART0 on the C8051T60x. The TX and RX signals of UART0 may be connected to the RS-232 transceiver by
installing shorting blocks on header J3. The RTS and CTS lines do not have a direct connection available to the
C8051T60x, due to limited pin resources on the device. However, these two signals have also been routed through
the transceiver, and are available for wiring on-board at test points near the DB-9 connector. The transceiver shifts
the UART signals to RS-232 levels, and connects to the appropriate pins on the DB-9 connector.
J3[1–2] - Install shorting block to connect UART0 RX (P0.5) to transceiver.
J3[3–4] - Install shorting block to connect UART0 TX (P0.4) to transceiver.
7.6. Analog I/O (J6)
Two of the C8051T60x target device's port pins are connected to the J6 terminal block. Refer to Table 3 for the J6
terminal block connections.
8
Table 2. J8 Pin Descriptions
Pin # Description
1 +3VD (+3.3 VDC)
2
3
4
5
6
7
8
9
10
11
12
Table 3. J6 Terminal Block Pin Descriptions
Pin # Description
1 GND (Ground)
2 P0.1/AIN1
3 P0.0/VREF
4
Rev. 0.1
VPP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
GND
/RST
VDD