Motorola MVME2600 Series Programmer's Reference Manual page 16

PowerPC 60x Bus to DRAM Access Timing When ConÞgured for 50ns Hyper De-
vices 3-10
PowerPC 60x Bus to ROM/Flash Access Timing When ConÞgured for 32/64-bit
Devices 3-11
PowerPC 60x Bus to ROM/Flash Access Timing When ConÞgured for 8-bit De-
vices 3-11
Error Reporting 3-14
PowerPC 60x to ROM/Flash Address Mapping with Two 8-bit Devices 3-18
PowerPC 60x Address to ROM/Flash Address Mapping with Two 32-bit or One
64-bit Device(s) 3-19
Register Summary 3-30
ram spd1,ram spd0 and DRAM Type 3-34
Block_A/B/C/D ConÞgurations 3-36
rtest encodings 3-44
ROM Block A Size Encoding 3-46
rom_a_rv and rom_b_rv encoding 3-47
Read/Write to ROM/Flash 3-48
ROM Block B Size Encoding 3-50
Sizing Addresses 3-57
PowerPC 60x Address to DRAM Address Mappings 3-58
Syndrome Codes Ordered by Bit in Error 3-59
Single-Bit Errors Ordered by Syndrome Code 3-60
PowerPC Data to DRAM Data Mapping 3-63
Universe Register Map 4-9
PCI Arbitration Assignments 5-1
RavenMPIC Interrupt Assignments 5-3
PIB PCI/ISA Interrupt Assignments 5-6
Reset Sources and Devices Affected 5-9
Error NotiÞcation and Handling 5-10
ROM/FLASH Bank Default 5-16
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