Motorola MVME2600 Series Programmer's Reference Manual page 11

Cache Coherency Restrictions 3-13
L2 Cache Support 3-13
ECC 3-13
Cycle Types 3-13
Error Reporting 3-14
Error Logging 3-15
DRAM Tester 3-15
ROM/Flash Interface 3-16
Refresh/Scrub 3-20
Blocks A and/or B Present, Blocks C and D Not Present 3-20
Blocks A and/or B Present, Blocks C and/or D present 3-21
DRAM Arbitration 3-22
Chip Defaults 3-22
External Register Set 3-23
CSR Accesses 3-23
Programming Model 3-24
CSR Architecture 3-24
Register Summary 3-29
Detailed Register Bit Descriptions 3-32
Vendor/Device Register 3-33
Revision ID/ General Control Register 3-33
DRAM Attributes Register 3-35
DRAM Base Register 3-37
CLK Frequency Register 3-37
ECC Control Register 3-38
Error Logger Register 3-41
Error_Address Register 3-43
Scrub/Refresh Register 3-43
Refresh/Scrub Address Register 3-44
ROM A Base/Size Register 3-45
ROM B Base/Size Register 3-48
DRAM Tester Control Registers 3-51
32-Bit Counter 3-51
Test SRAM 3-52
Power-Up Reset Status Register 1 3-53
Power-Up Reset Status Register 2 3-53
External Register Set 3-54
Software Considerations 3-55
Parity Checking on the PowerPC Bus 3-55
Programming ROM/Flash Devices 3-55
Writing to the Control Registers 3-55