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S3C9442/C9444/F9444/C9452/C9454/F9454
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Port 0 control register (High byte)
Port 0 control register
Port 0 interrupt pending register
Port 1 control register
Port 2 control register (High byte)
Port 2 control register (Low byte)
PWM data register
PWM control register
STOP .control register
A/D control register
A/D converter data register ( High )
A/D converter data register ( Low )
NOTE: – : Not mapped or not used, x: Undefined
Table 4-1. System and Peripheral Control Registers (Continued)
Mnemonic
Locations E3H–E5H are not mapped
P0CONH
P0CONL
P0PND
P1CON
P2CONH
P2CONL
Locations ECH–F1H are not mapped
PWMDATA
PWMCON
STOPCON
Locations F5H–F6H are not mapped
ADCON
ADDATAH
ADDATAL
Locations FAH–FFH are not mapped
Address
Hex
P0
E0H
P1
E1H
P2
E2H
E6H
E7H
E8H
E9H
EAH
EBH
F2H
F3H
F4H
F7H
F8H
F9H
CONTROL REGISTERS
R/W
Bit Values After RESET
7
6
5
4
R/W
0
0
0
0
R/W
–
–
–
–
R/W
–
0
0
0
R/W
0
0
0
0
R/W
0
0
0
0
R/W
–
–
–
–
R/W
0
0
–
–
R/W
–
0
0
0
R/W
0
0
0
0
R/W
0
0
0
0
R/W
0
0
–
0
R/W
0
0
0
0
R/W
0
0
0
0
R
x
x
x
x
R
0
0
0
0
3
2
1
0
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
0
0
x
x
4-3
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