Infineon PSoC 4000 Series Technical Reference Manual page 34

1.1.25 CM0_ISPR
Address = 0xE000E200
Interrupt Set-Pending Register
Address: 0xE000E200
Retention: Retained
Bits 7
SW Access
HW Access
Name
Bits 15
SW Access
HW Access
Name
Bits 23
SW Access
HW Access
Name
Bits 31
SW Access
HW Access
Name
Bits Name
31 : 0 SETPEND
PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E
6 5 4
SETPEND [7:0]
14 13 12
SETPEND [15:8]
22 21 20
SETPEND [23:16]
30 29 28
SETPEND [31:24]
Description
Changes the state of one or more interrupts to pending. Each bit corresponds to the same num-
bered interrupt.
Default Value: 0
3 2
RW1S
R
11 10
RW1S
R
19 18
RW1S
R
27 26
RW1S
R
CM0_ISPR
1 0
9 8
17 16
25 24
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