Termination And Pull-Up/Pull-Down Resistors; Changes To Decoupling And Reservoir Capacitors Section And Board Internal Layer Thickness Section; Added Overlapping Stitching Capacitor Section And Pcb Layout Recommendation Section; Decoupling And Reservoir Capacitors - Analog Devices EVAL-ADM2582EEBZ User Manual

UG-044
TERMINATION AND PULL-UP/PULL-DOWN
RESISTORS
The evaluation board includes the RT and RT1 footprints for
fitting termination resistors between the A and B receiver inputs
and the Y and Z driver outputs. By default, the board is not fitted
with a 120 Ω resistor, RT, between A and B. This resistor must
not be fitted if the board is connected to a bus that is already
terminated at both ends. For more information about proper
termination, see the AN-960 Application
Circuit Implementation Guide.
Although the ADM2582E/ADM2587E
fail-safe for the bus idle condition, there are footprints on the
evaluation board for fitting the R9 and R10 pull-up resistors to
the V supply of the
ISOOUT
Input A and Driver Output Y, as well as the R7 and R8 pull-
down resistors to GND
2
These resistors can be fitted if the user is connecting to other
devices that require external biasing resistors on the bus. The
exact value required for a 200 mV minimum differential voltage
in the bus idle condition depends on the supply voltage (for
example, 960 Ω for 3.3 V and 1440 Ω for 5 V).
For more information about the bus idle fail-safe, see the
Note, RS-485/RS-422 Circuit Implementation Guide.
Application

DECOUPLING AND RESERVOIR CAPACITORS

The evaluation board uses the following decoupling and
reservoir capacitors:
•
On the logic side of the board, the C3 and C4 capacitors
must be 10 nF and 100 nF ceramic capacitors, respectively,
and the C2 capacitor must be a 10 µF tantalum capacitor.
•
On the logic side of the board, the C7 capacitor must be a
100 nF ceramic capacitor, and the C9 capacitor must be a
10 µF tantalum capacitor.
•
On the logic side of the board, additional capacitors are
added for the power regulation circuits. C12, C13, and C16
must be 10 µF tantalum capacitors, and C14 and C15 must
be 100 nF ceramic capacitors.
•
On the bus side of the board, the C5 and C6 capacitors must
be 10 nF and 100 nF, respectively, and the C1 and C8
capacitors must be 100 nF and 10 µF, respectively.

BOARD INTERNAL LAYER THICKNESS

The EVAL-ADM2582EEBZ/EVAL-ADM2587EEBZ
board consists of four layers. The spacing between the top and
bottom layer is 1.6 mm.
The EVAL-ADM2582EEBZ
a minimum distance of 0.4 mm of insulation along a bonded
surface, meeting requirements for isolation standards IEC 61010,
third edition, and IEC 60950 as described in the
Application Note, Recommendations for Control of Radiated
Emissions with iCoupler® Devices.
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EVAL-ADM2582EEBZ/EVAL-ADM2587EEBZ User Guide
Note, RS-485/RS-422
have a built in receiver
ADM2582E/ADM2587E on Receiver
on Receiver Input B and Driver Output Z.
evaluation
and EVAL-ADM2587EEBZ
AN-1109

OVERLAPPING STITCHING CAPACITOR

The evaluation board implements an embedded stitching capacitor
structure. An embedded PCB capacitor is created when two metal
planes in a PCB overlap each other and are separated by dielectric
material. This embedded stitching capacitor is formed by extending
the internal reference planes from the primary and secondary
layers across the area, which is used for creepage on the PCB
surface. This capacitor provides a return path for high frequency
common-mode noise currents across the isolation gap. The
overlapping area is 53 mm × 7 mm and the distance between
overlapping layers is 0.4064 mm, therefore, the plate capacitor is
around 35 pF. The layout and implementation of embedded
stitching capacitors is explained in detail in the
Application

PCB LAYOUT RECOMMENDATIONS

The EVAL-ADM2582EEBZ/EVAL-ADM2587EEBZ
board is designed to reduce emissions generated by the high
frequency switching elements used by the isoPower technology
to transfer power through the
transformer. The layout of the evaluation board is generated using
the guidelines provided in the
AN-960
The AN-1349 Application Note
The EVAL-ADM2582EEBZ
layouts are 4-layer PCBs. To pass EN55022 Class B on a 4-layer
PCB, the following layout guidelines are recommended:
•
Ensure that there is good decoupling on the PCB (see the
Decoupling and Reservoir Capacitors section).
•
Place a ferrite bead between the PCB trace connections and
the following IC pins: V
and Pin 14).
•
Do not connect the V
between V
V (Pin 19) is connected through the L3 ferrite to V
ISOIN
(Pin 12), as shown in Figure 3.
•
Place an embedded stitching capacitor between GND
GND
2
Overlapping Stitching Capacitor section).
The following additional notes apply to the PCB layout; refer to
the schematic and artwork in Figure 8 to Figure 13.
•
Ensure that GND
on the inside (device side) of the C1 100 nF capacitor.
•
Ensure that the C1 capacitor is connected between V
(Pin 12) and GND
and L3 ferrites.
PCB has
•
Ensure that GND
on the outside (bus side) of the L2 ferrite, as shown in
Figure 3.
•
Ensure that there is a keep out area for the GND
the PCB layout around the L2 and L3 ferrites. The keep out
area means there must not be a GND
below the L2 and L3 ferrites.
Rev. D | Page 4 of 13
Note.
ADM2582E/ADM2587E
AN-1349 Application
provides examples of 4-layer PCBs.
and EVAL-ADM2587EEBZ
(Pin 12) and GND
ISOOUT
pin to a power plane; connect
ISOOUT
and V using a PCB trace. Ensure that
ISOOUT ISOIN
using internal layers of the PCB planes (see the
(Pin 14) is connected to GND
2
(Pin 11) on the device side of the L2
2
(Pin 16) is connected to GND
2
AN-0971
evaluation
integrated
Note.
PCB
(Pin 11
2
ISOOUT
and
1
(Pin 11)
2
ISOOUT
(Pin 11)
2
plane in
2
fill on any layer
2