Event Generation Registers (Timx_Evtgen) - Nations N32G430 Series User Manual

Bit field Name

Event generation registers (TIMx_EVTGEN)

Offset address: 0x14
Reset values: 0x0000
Bit field Name
15：8 Reserved
7 BGN
6 TGN
5 CCUDGN
4 CC4GN
3 CC3GN
2 CC2GN
Description
1: Update interrupt occurred
Description
Reserved, the reset value must be maintained
Break generation
This bit can generate a brake event when set by software. And at this time TIMx_BKDT.MOEN =
0, TIMx_STS.BITF = 1, if the corresponding interrupt and DMA are enabled, the corresponding
interrupt and DMA will be generated. This bit is automatically cleared by hardware.
0: No action
1: Generated a break event
Trigger generation
This bit can generate a trigger event when set by software. And at this time TIMx_STS.TITF = 1, if
the corresponding interrupt and DMA are enabled, the corresponding interrupt and DMA will be
generated. This bit is automatically cleared by hardware.
0: No action
1: Generated a trigger event
Capture/Compare control update generation
This bit is set by software. And if TIMx_CTRL2.CCPCTL = 1 at this time, the CCxEN, CCxNEN
and OCxMD bits are allowed to be updated. This bit is automatically cleared by hardware.
0: No action
1: Generated a COM event
Note: This bit is only valid for channels with complementary outputs.
Capture/Compare 4 generation
See TIMx_EVTGEN.CC1GN description.
Capture/Compare 3 generation
See TIMx_EVTGEN.CC1GN description.
Capture/Compare 2 generation
See TIMx_EVTGEN.CC1GN description.
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