Dma Channel X Peripheral Address Register (Dma_Paddrx); Dma Channel X Memory Address Register (Dma_Maddrx) - Nations N32G430 Series User Manual

Bit field Name
31:16 Reserved
15:0 NDTX

DMA channel x peripheral address register (DMA_PADDRx)

Note：The x is channel number, x = 1...8
Address offset: 0x10+20 * (x–1)
Reset value: 0x0000 0000
This register can only be written if the channel is disabled (DMA_CHCFGx.CHEN = 0).
Bit field Name
31:0 ADDR

DMA channel x memory address register (DMA_MADDRx)

Note：The x is channel number, x = 1...8
Address offset: 0x14+20 * (x–1)
Reset value: 0x0000 0000
This register can only be written if the channel is disabled (DMA_CHCFGx.CHEN = 0).
Description
Reserved, the reset value must be maintained.
Number of data to transfer.
Number of data to be transferred (0～65535). Software can read/write the number of
transfers when channel is disable and it will be read only after channel enable. Every
successful transfer of corresponding DMA channel will decrease this register by 1. If
circular mode is enable, it will automatically reload pre-set value when it reach zero.
Otherwise it will keep at zero and reset channel enable.
Description
Peripheral address.
Peripheral starting address for DMA to read/write from/to.
Increment of address will be decided by DMA_CHCFGx.PSIZE. With
DMA_CHCFGx.PSIZE equal to 01, DMA ignores bit 0 of PADDR and if
DMA_CHCFGx.PSIZE equal to 10 DMA will ignore bit [1:0] of PADDR.
204 / 647
Nations Technologies Inc.
Tel：+86-755-86309900
Email：info@nationstech.com
Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China