Interrupt Request Pending Register(Exti_Pend); Rtc Timestamp Selection Register(Exti_Ts_Sel) - Nations N32G430 Series User Manual

Bit field Name
31:24 Reserved
23:0 SWIEx

Interrupt Request Pending Register(EXTI_PEND)

Address offset : 0x14
Reset value : 0x00000000
Bit field Name
31:24 Reserved
23:0 PENDx

RTC Timestamp Selection Register(EXTI_TS_SEL)

Address offset : 0x18
Reset value : 0x00000000
Description
Reserved, the reset value must be maintained.
Software interrupt on line x
When this bit is '0', writing '1' will set the corresponding pengding bit in
EXTI_PEND. If this interrupt is allowed in EXTI_IMASK and EXTI_EMASK, an
interrupt will be generated at this time.
Note: By writing '1' to clear the corresponding bit of EXTI_PEND, this bit can be
cleared to '0'.
Description
Reserved, the reset value must be maintained.
Hang bit on line x
0: No pending request occurred.
1: A pending trigger request has occurred.
This bit is set to '1' when a selected edge trigger event occurs on the external interrupt
line. Write '1' in this bit to clear it, or change the polarity of edge detection to clear
this bit.
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