Capture/Compare Mode Register 2 (Timx_Ccmod2) - Nations N32G430 Series User Manual

Bit field Name
3:2 IC1PSC[1:0]
1:0 CC1SEL[1:0]

Capture/compare mode register 2 (TIMx_CCMOD2)

Offset address: 0x1C
Reset value: 0x0000 0000
See the description of the CCMOD1 register above
Output comparison mode:
31
Reserved
15 14 12
OC4CEN OC4MD[2:0]
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Description
0100: f = f /2, N = 6
SAMPLING DTS
0101: f = f /2, N = 8
SAMPLING DTS
0110: f = f /4, N = 6
SAMPLING DTS
0111: f = f /4, N = 8
SAMPLING DTS
1000: f = f /8, N = 6
SAMPLING DTS
1001: f = f /8, N = 8
SAMPLING DTS
1010: f = f /16, N = 5
SAMPLING DTS
1011: f = f /16, N = 6
SAMPLING DTS
1100: f = f /16, N = 8
SAMPLING DTS
1101: f = f /32, N = 5
SAMPLING DTS
1110: f = f /32, N = 6
SAMPLING DTS
1111: f = f /32, N = 8
SAMPLING DTS
Input Capture 1 prescaler
These bits are used to select the ratio of the prescaler for IC1 (CC1 input).
When TIMx_CCEN.CC1EN = 0, the prescaler will be reset.
00: No prescaler, capture is done each time an edge is detected on the capture input
01: Capture is done once every 2 events
10: Capture is done once every 4 events
11: Capture is done once every 8 events
Capture/Compare 1 selection
These bits are used to select the input/output and input mapping of the channel
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped to TRC. This mode is only active when the
internal trigger input is selected by TIMx_SMCTRL.TSEL.
Note: CC1SEL is writable only when the channel is off (TIMx_CCEN.CC1EN = 0).
27 26 25
OC9PEN
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11 10 9 8
OC4PEN OC4FEN CC4SEL[1:0]
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275 / 647
22 21
Reserved OC8PEN
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7 6
OC3CEN OC3MD[2:0]
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20 17
Reserved
4 3 2 1
OC3PEN OC3FEN CC3SEL[1:0]
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16
OC7PEN
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0
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