Power Control Status Register (Pwr_Ctrlsts) - Nations N32G430 Series User Manual

Bit field Name
0 LPS

Power control status register (PWR_CTRLSTS)

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from STANDBY mode)
Additional APB cycles are needed to read this register versus a standard APB read.
Bit field Name
31:15 Reserved
14 WKUP3PS
13 WKUP2PS
12 WKUP1PS
11 WKUPRTCEN
10 WKUP3EN
Description
Software will set and clear this bit and config together with PWR_CTRL.LPS.
0: Enter stop mode when the CPU enters deep-sleep. The regulator status depends on
PWR_CTRL.LPS.
1: Enter STANDBY mode when the CPU enters deep-sleep mode.
Low-power deep-sleep.
Software will set and clear this bit and config together with PWR_CTRL.PDS.
0: Voltage regulator on during stop mode.
1: Voltage regulator in low-power mode during stop mode.
Description
Reserved, the reset value must be maintained.
Wakeup polarity selection for PC13.
To wakeup STANDBY mode by using rising edge or falling edge. Make sure disable
wakeup enable before changing polarity value.
0: Rising edge
1: Falling edge
Wakeup polarity selection for PA0.
To wakeup STANDBY mode by using rising edge or falling edge. Make sure disable
wakeup enable before changing polarity value.
0: Rising edge
1: Falling edge
Wakeup polarity selection for PA8.
To wakeup STANDBY mode by using rising edge or falling edge. Make sure disable
wakeup enable before changing polarity value.
0: Rising edge
1: Falling edge
RTC internal wakeup enable
0: Wakeup is disabled
1: Wakeup is enabled
Enable PC13_WKUP pin
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