Trigger Out; Trigger Out Latency - THORLABS KBD101 User Manual

Chapter 4

4.5.3 Trigger Out

The TRIG output is the output of a standard 5V CMOS logic gate in series with a 470
resistor. The resistor provides protection against accidentally short circuiting to
ground by limiting the current to approx 10 mA maximum.
Do not connect the output to any voltage level outside the 0 to 5V range. It is
recommended that the output is only used to drive external devices or equipment that
has a high input resistance (>10 k).

4.5.4 Trigger Out Latency

The detection of whether a trigger condition has occurred is carried out periodically at
102 µs intervals. As a result, there is a maximum 102 µs delay between the condition
occurring and the trigger output being updated. The following timing diagram
illustrates this latency:
Trigger condition occurs
Trigger condition sampled at 102 μs intervals
30
CMOS Logic Gate
Protection
Fig. 4.4 TRIG OUT Connection Detail
Trigger output updated
Fig. 4.5 Triggering Latency
470R
HA0364T Rev C Aug 2022
SMA
Connector
0V
time
time
time