Pci Express Slot 1 (Peg1) - Avalue Technology EAX-R680P User Manual

EAX-R680P User's Manual
PCIe Speed
Detect Timeout
3.6.3.1.5.2

PCI Express Slot 1 (PEG1)

Item
PCI Express Slot 1 (PEG1)
ASPM
L1 Substates
PCIe Speed
Detect Timeout
62 EAX-R680P User's Manual
L1.1
L1.1 & L1.2[Default]
Auto[Default]
/Gen1/Gen2
/Gen3/Gen4/Gen5
0
Option
Disabled
Enabled[Default],
Disabled[Default]
L0s
L1
L0sL1
Disabled
L1.1
L1.1 & L1.2[Default]
Auto[Default]
/Gen1/Gen2
/Gen3/Gen4/Gen5
0
cannot be enabled when CLKREQMSG is
disabled
Configure PCIe Speed
The number of milliseconds reference code
will wait for link to exit Detect state for
enabled ports before assuming there is no
device and potentially disabling the port.
Description
Control the PCI Express Root Port.
Set the ASPM Level: Force L0s - Force all
links to L0s State AUTO - BIOS auto
configure DISABLE - Disables ASPM
PCI Express L1 Substates settings.L1SS
cannot be enabled when CLKREQMSG is
disabled
Configure PCIe Speed
The number of milliseconds reference code
will wait for link to exit Detect state for
enabled ports before assuming there is no
device and potentially disabling the port.