Sound Control Circuit - Sanyo AVM-2550S Training Manual

The sound level is controlled by the BUS control signal form the CPU, the
BUS SDA (Serial Data) signal from pin 32, and the BUS SCL (Serial Clock)
signal from pin 34. The BUS control signals from the CPU are coupled to the
BUS Interface circuit within IC3401, the MTS Processor. The BUS Interface
circuit transfers a 6-bit volume data into both of the Volume Control Registers
VOL-L and VOL-R. A 6-bit volume control data from each of the Volume
Control Registers is converted to a 0-63 steps analog signal (DC voltages) in
the Volume D/A converter for input to the Volume Control Circuit. Now the
audio signal is output from pins 3 and 4 of IC3401.
STA
(MSB)
D7 D6 D5 D4 D3
1 0 0 0 0
IC WRITE ADDRESS
(MSB)
D7 D6 D5 D4 D3
1 0 0 0 0
IC WRITE ADDRESS

SOUND CONTROL CIRCUIT

ICW SUB
(LSB) (MSB)
D2 D1 D0 D7 D6
1 0 0 0 0
(LSB) (MSB)
D2 D1 D0 D7 D6
1 0 0 0 0
BUS Data Format in Write Mode - Volume Level at 16/63 step
The volume control data "000000" and the audio mute control data "0" are
input to the Volume Control Registers VOL-L and VOL-R, and the Audio Mute
Control Register M2 (Sub Address 03h, Bit 6), respectively to set the output
sound level to step 0/63 during Mute ON. (See page 30 for the Audio Mute
Control Register M2.)
In addition, the CPU outputs the Mute (High) signal from pin 38 to prevent
buzz or static in the speakers when turning On/Off or during Standby mode.
The Mute (High) is coupled to the base of Q001, switching Q001 On,
grounding pin 5 of the Audio Amplifier IC001.
DA
(LSB) (MSB)
D5 D4 D3 D2 D1
0 0 0 1 1
SUB. ADDRESS
(LSB) (MSB)
D5 D4 D3 D2 D1
0 0 1 0 0
SUB. ADDRESS
– 18 –
STA: START Condition
ICW: IC Address + Write
STO
SUB: Sub. Address
DA : Data
STO: STOP Condition
D0 DA7 DA6 DA5 DA4 DA3
1 0 1
Don't care bits
D0 DA7 DA6 DA5 DA4 DA3
0 0 1
Don't care bits
(LSB)
DA2 DA1 DA0
0 0 0 0
VOL-L
(LSB)
DA2 DA1 DA0
0 0 0 0
VOL-R