Caption Data Slicer - Sanyo AVM-2550S Training Manual

The Data Slicer extracts the caption data encoded on ling 21, field 1 (odd) of
the composite video signal for input into the OSD Controller included in the
CPU. The Data Slicer also generates the necessary clock and synchronizing
signals required for decoding the data.
Operation:
CLAMP CIRCUIT, LOW PASS FILTER
Composite video (2 Vp-p) is AC coupled to the CPU on pin 17 and clamped
by an internal clamp circuit. The clamp circuit clamps the sync tips of the
video to a fixed reference voltage to provide a degree of noise rejection. From
the clamp circuit the composite signal is coupled to the Low Pass Filter to
attenuate the noise within the composite signal.
SYNC SLICER
The composite signal from the Low Pass Filter is coupled to the Sync Slicer
and the composite sync signal extracted from the composite video signal.

CAPTION DATA SLICER

Composite
Sync Signal
Timing Signal
Vsep Signal
Timing of Generating Vsep Signal
SYNC SEPARATOR, TIMING GENERATOR
The composite sync signal from the Sync Slicer is input to the Sync Separator
and separated into the horizontal sync signal (Hsep) and the vertical sync
signal (Vsep).
The Timing Signal Generator controlled by the Data Slicer Control Registers
1-2 generates a reference clock signal with a clock rate of 13.0832MHz
(832fH). The clock signal, the separated horizontal sync signal and the
separated vertical sync signal are used to generate other timing signals
required for the Data Slicer. The reference clock signal generated from the
Timing Signal Generator is also used as the clock for the OSD Controller.
The horizontal sync signal (Hsep) is generated and synchronized with the
horizontal sync signal within the composite sync signal. The vertical sync
signal (Vsep) is generated at the first rising point of the timing signal and a
certain period of time has past after the composite sync signal has become a
Low level (see Figure below).
Vsep is generated at this rising point.
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