Mts Processor Bus Control Circuits - Sanyo AVM-2550S Training Manual

The VB7C chassis is equipped with a new single-chip BUS-Controlled MTS
Processor IC to replace much of the mechanically adjusted factory/service
controls and all of the low pass filters in the PWM control lines for the
customer setting digital controls used in the conventional chassis. In addition,
the Bass, Treble and Volume control circuits have been also integrated into a
single-chip IC.
The primary difference between this chassis and the conventional chassis is
the addition of the BUS Interface circuit and movement of the control registers
into the MTS Processor IC, and the BUS control program incorporated in the
CPU (C-003).
The advantages of this chassis include reduced control lines and associated
circuitry, and improved productivity and increased accuracy of the factory
adjustments during production. This is due to the computerized and digitized
control circuit which allows remote operation.
IC801
CPU
L881
BUS
32
SDA
L882
BUS
34
SCL
MTS Processor BUS Control Circuit
MTS PROCESSOR BUS CONTROL CIRCUIT
IC3401
MTS PROCESSOR
R881 R3401
5
SDA
BUS
Interface
R3402
R882
6
SCL
Control
Registers
Control of the MTS Processor IC is through CPU pins 32 and 34.
Pin 34 is the BUS SCL (Serial Clock) signal. The BUS SCL input is used to
clock all data into and out of IC101.
Pin 32 is the BUS SDA (Serial Data) signal. The BUS SDA is a bi-directional
signal and is used to transfer data into and out of the control registers within
IC3401. Data is processed through an 8-bit read or write for each sub
address in an IC address "10000100" (Read Address) or "10000101" (Write
Address) within IC3401.
STA ICA
STA = START Condition
ICA = IC Address* + Read or Write
SUB = Sub. Address* (needed only in Write mode)
DA = Data*
STO = STOP Condition
* See Bit Map below for IC Address,
See Bit Map below for IC Address, c
Sub Address or Data for details. Sub Address or Data for details.
BUS Data Format in Write Mode
– 16 –
SUB DA STO