Aft Defeat Circuit - Sanyo AVM-2550S Training Manual

The AFT Defeat circuit is provided to reduce interference or "tweet" in the
video produced by the AFT circuitry. Since the AFT function is needed only
when changing channels, the AFT can be disabled at all other times.
The AFT enabling/disabling is controlled by the BUS control signal from the
CPU: the BUS SDA (Serial Data) signal from pin 32, and the BUS SCL (Serial
Clock) signal from pin 34. Normally the CPU outputs the BUS control signal
to disable the AFT circuitry. The BUS control signal from the CPU are input
to the BUS interface circuit within IC101, the Signal Processor. The BUS
interface circuit will write a 1 bit data "1" into the AFT Defeat Control Register
STA
(MSB)
D7 D6 D5 D4 D3
1 0 1 1 1
IC WRITE ADDRESS

AFT DEFEAT CIRCUIT

ICW SUB
(LSB) (MSB)
D2 D1 D0 D7 D6
0 1 0 0 0
BUS Data Format in Write Mode - AFT Defeat Operation
to turn off the AFT Amplifier, then the AFT output voltage at pin 13 of IC101
will be fixed to 1/2Vcc (approx. 3.8VDC). When changing channels, the AFT
enabling BUS data is input to the BUS Interface circuit to write a 1 bit data "0"
into the AFT Defeat Control Register, allowing the AFT circuit to operate.
An additional adjustment mode is provided for the service adjustment to
disable the AFT Circuitry continuously for adjusting the APC DET and PLL
Tuning. When you enter the APC DET or PLL Tuning adjustment mode in the
service menu, the CPU will automatically output the BUS data to disable the
AFT circuitry continuously.
DA
(LSB)
D5 D4 D3 D2 D1
0 0 0 0 1
SUB. ADDRESS
– 32 –
STA: START Condition
ICW: IC Address + Write
STO
SUB: Sub. Address
DA : Data
STO: STOP Condition
(MSB)
D0 DA7 DA6 DA5 DA4 DA3
0 0 1 0 1
IF AGC RF AGC DELAY
AFT
DEFEAT
(LSB)
DA2 DA1 DA0
1 0 0 1