NXP Semiconductors MK53DX256ZCLQ10 Manuals

Manuals and User Guides for NXP Semiconductors MK53DX256ZCLQ10. We have 1 NXP Semiconductors MK53DX256ZCLQ10 manual available for free PDF download: Reference Manual

NXP Semiconductors MK53DX256ZCLQ10 Reference Manual (1823 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 20 MB

Table of Contents
3
About this Document
59
Overview
59
Purpose
59
Audience
59
Conventions
59
Numbering Systems
59
Typographic Notation
60
Special Terms
60
Introduction
61
Overview
61
K50 Family Introduction
61
Module Functional Categories
61
ARM Cortex-M4 Core Modules
63
System Modules
63
Memories and Memory Interfaces
64
Clocks
65
Security and Integrity Modules
66
Analog Modules
66
Timer Modules
66
Communication Interfaces
68
Human-Machine Interfaces
68
Orderable Part Numbers
69
Chip Configuration
71
Introduction
71
Core Modules
71
ARM Cortex-M4 Core Configuration
71
Nested Vectored Interrupt Controller (NVIC) Configuration
74
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
80
JTAG Controller Configuration
81
System Modules
82
SIM Configuration
82
Mode Controller Configuration
83
PMC Configuration
83
Low-Leakage Wake-Up Unit (LLWU) Configuration
84
MCM Configuration
86
Crossbar Switch Configuration
86
Memory Protection Unit (MPU) Configuration
89
Peripheral Bridge Configuration
91
DMA Request Multiplexer Configuration
93
DMA Controller Configuration
96
External Watchdog Monitor (EWM) Configuration
97
Watchdog Configuration
98
Clock Modules
99
MCG Configuration
99
OSC Configuration
100
RTC OSC Configuration
101
Memories and Memory Interfaces
101
Flash Memory Configuration
101
Flash Memory Controller Configuration
105
SRAM Configuration
106
SRAM Controller Configuration
110
Analog
118
16-Bit SAR ADC with PGA Configuration
118
CMP Configuration
126
12-Bit DAC Configuration
128
Op-Amp Configuration
129
TRIAMP Configuration
131
VREF Configuration
132
Timers
133
PDB Configuration
133
Flextimer Configuration
137
PIT Configuration
140
Low-Power Timer Configuration
141
CMT Configuration
143
RTC Configuration
144
Communication Interfaces
145
Ethernet Configuration
145
Universal Serial Bus (USB) Subsystem
147
SPI Configuration
153
I2C Configuration
156
UART Configuration
157
SDHC Configuration
159
I2S Configuration
160
Human-Machine Interfaces (HMI)
162
GPIO Configuration
162
TSI Configuration
163
Segment LCD Configuration
166
Memory Map
169
Introduction
169
System Memory Map
169
Aliased Bit-Band Regions
170
Flash Memory Map
171
Alternate Non-Volatile IRC User Trim Description
172
SRAM Memory Map
173
Peripheral Bridge (AIPS-Lite0 and AIPS-Lite1) Memory Maps
173
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
173
Peripheral Bridge 1 (AIPS-Lite 1) Memory Map
177
Private Peripheral Bus (PPB) Memory Map
182
Clock Distribution
183
Introduction
183
Programming Model
183
High-Level Device Clocking Diagram
183
Clock Definitions
184
Device Clock Summary
185
Internal Clocking Requirements
187
Clock Divider Values after Reset
188
VLPR Mode Clocking
188
Clock Gating
189
Module Clocks
189
PMC 1-Khz LPO Clock
191
WDOG Clocking
191
Debug Trace Clock
191
PORT Digital Filter Clocking
192
LPTMR Clocking
192
Ethernet Clocking
193
USB FS OTG Controller Clocking
194
UART Clocking
194
SDHC Clocking
194
I2S Clocking
195
TSI Clocking
195
Reset and Boot
197
Introduction
197
Reset
197
Power-On Reset (POR)
198
System Resets
198
Debug Resets
202
Boot
203
Boot Sources
203
Boot Options
203
FOPT Boot Options
203
Boot Sequence
204
Power Management
207
Introduction
207
Power Modes
207
Entering and Exiting Power Modes
209
Power Mode Transitions
210
Power Modes Shutdown Sequencing
211
Module Operation in Low Power Modes
211
Clock Gating
214
Security
215
Introduction
215
Flash Security
215
Security Interactions with Other Modules
216
Security Interactions with Flexbus
216
Security Interactions with Ezport
216
Security Interactions with Debug
216
Introduction
219
References
221
The Debug Port
221
JTAG-To-SWD Change Sequence
222
JTAG-To-Cjtag Change Sequence
222
Debug Port Pin Descriptions
223
System TAP Connection
223
IR Codes
224
JTAG Status and Control Registers
224
MDM-AP Control Register
225
MDM-AP Status Register
227
Debug Resets
228
Ahb-Ap
229
Itm
230
Core Trace Connectivity
230
Embedded Trace Macrocell V3.5 (ETM)
230
Coresight Embedded Trace Buffer (ETB)
231
Performance Profiling with the ETB
231
ETB Counter Control
232
Tpiu
232
Dwt
232
Debug in Low Power Modes
233
Debug Module State in Low Power Modes
234
Debug & Security
234
Signal Multiplexing and Signal Descriptions
235
Introduction
235
Signal Multiplexing Integration
235
Port Control and Interrupt Module Features
236
Clock Gating
236
Signal Multiplexing Constraints
236
Pinout
237
K53 Signal Multiplexing and Pin Assignments
237
K53 Pinouts
243
Module Signal Description Tables
245
Core Modules
246
System Modules
246
Clock Modules
247
Memories and Memory Interfaces
247
Analog
248
Communication Interfaces
250
Human-Machine Interfaces (HMI)
257
Port Control and Interrupts (PORT)
259
Introduction
259
Overview
259
Features
259
Modes of Operation
260
External Signal Description
261
Detailed Signal Descriptions
261
Memory Map and Register Definition
261
Pin Control Register N (Portx_Pcrn)
268
Global Pin Control Low Register (Portx_Gpclr)
270
System Clock Gating Control Register 6 (SIM_SCGC6)
300
System Clock Gating Control Register 7 (SIM_SCGC7)
302
System Clock Divider Register 1 (SIM_CLKDIV1)
303
System Clock Divider Register 2 (SIM_CLKDIV2)
306
Flash Configuration Register 1 (SIM_FCFG1)
307
Flash Configuration Register 2 (SIM_FCFG2)
309
Unique Identification Register High (SIM_UIDH)
310
Unique Identification Register MID-High (SIM_UIDMH)
311
Unique Identification Register MID Low (SIM_UIDML)
311
Unique Identification Register Low (SIM_UIDL)
312
Functional Description
312
Mode Controller
313
Introduction
313
Features
313
Modes of Operation
313
MCU Reset
324
Mode Control Memory Map/Register Definition
327
System Reset Status Register High (MC_SRSH)
328
System Reset Status Register Low (MC_SRSL)
329
Power Mode Protection Register (MC_PMPROT)
330
Power Mode Control Register (MC_PMCTRL)
332
Power Management Controller
335
Introduction
335
Features
335
Low-Voltage Detect (LVD) System
335
LVD Reset Operation
336
LVD Interrupt Operation
336
Low-Voltage Warning (LVW) Interrupt Operation
336
PMC Memory Map/Register Definition
337
Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
337
Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
338
Regulator Status and Control Register (PMC_REGSC)
340
Low-Leakage Wake-Up Unit (LLWU)
343
Introduction
343
Features
344
Modes of Operation
344
Block Diagram
345
LLWU Signal Descriptions
346
Memory Map/Register Definition
347
LLWU Pin Enable 1 Register (LLWU_PE1)
347
LLWU Pin Enable 2 Register (LLWU_PE2)
348
LLWU Pin Enable 3 Register (LLWU_PE3)
350
LLWU Pin Enable 4 Register (LLWU_PE4)
351
LLWU Module Enable Register (LLWU_ME)
352
LLWU Flag 1 Register (LLWU_F1)
353
LLWU Flag 2 Register (LLWU_F2)
355
LLWU Flag 3 Register (LLWU_F3)
357
LLWU Control and Status Register (LLWU_CS)
358
Functional Description
359
LLS Mode
360
VLLS Modes
360
Initialization
361
Low Power Mode Recovery
361
Miscellaneous Control Module (MCM)
363
Introduction
363
Features
363
Memory Map/Register Descriptions
363
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
364
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
364
SRAM Arbitration and Protection (MCM_SRAMAP)
365
Interrupt Status Register (MCM_ISR)
366
ETB Counter Control Register (MCM_ETBCC)
367
ETB Reload Register (MCM_ETBRL)
368
ETB Counter Value Register (MCM_ETBCNT)
369
Functional Description
369
Interrupts
369
Crossbar Switch (AXBS)
371
Introduction
371
Features
371
Memory Map / Register Definition
372
Priority Registers Slave (Axbs_Prsn)
373
Control Register (Axbs_Crsn)
376
Master General Purpose Control Register (Axbs_Mgpcrn)
378
Functional Description
379
General Operation
379
Register Coherency
380
Arbitration
380
Initialization/Application Information
383
Memory Protection Unit (MPU)
385
Introduction
385
Introduction
425
Features
426
Modes of Operation
426
External Signal Description
427
Memory Map/Register Definition
427
Channel Configuration Register (Dmamux_Chcfgn)
428
Functional Description
429
DMA Channels with Periodic Triggering Capability
429
DMA Channels with no Triggering Capability
432
Always Enabled" DMA Sources
432
Initialization/Application Information
433
Reset
433
Enabling and Configuring Sources
433
Direct Memory Access Controller (Edma)
437
Introduction
437
Block Diagram
437
Block Parts
438
Features
440
Modes of Operation
441
Memory Map/Register Definition
441
Control Register (DMA_CR)
456
Error Status Register (DMA_ES)
458
Enable Request Register (DMA_ERQ)
460
Enable Error Interrupt Register (DMA_EEI)
462
Clear Enable Error Interrupt Register (DMA_CEEI)
464
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
491
Functional Description
492
Edma Basic Data Flow
492
Error Reporting and Handling
495
Channel Preemption
497
Performance
497
Initialization/Application Information
502
Edma Initialization
502
Programming Errors
504
Arbitration Mode Considerations
504
Performing DMA Transfers
505
Monitoring Transfer Descriptor Status
509
Channel Linking
511
Dynamic Programming
512
External Watchdog Monitor (EWM)
515
Introduction
515
Features
515
Modes of Operation
516
Block Diagram
517
EWM Signal Descriptions
518
Memory Map/Register Definition
518
Control Register (EWM_CTRL)
518
Service Register (EWM_SERV)
519
Compare Low Register (EWM_CMPL)
520
Compare High Register (EWM_CMPH)
520
Functional Description
521
The Ewm_Out Signal
521
The Ewm_In Signal
522
EWM Counter
522
EWM Compare Registers
522
EWM Refresh Mechanism
523
Watchdog Timer (WDOG)
525
Introduction
525
Features
525
Functional Overview
527
Unlocking and Updating the Watchdog
528
The Watchdog Configuration Time (WCT)
529
Refreshing the Watchdog
530
Windowed Mode of Operation
530
Watchdog Disabled Mode of Operation
530
Low Power Modes of Operation
531
Debug Modes of Operation
531
Testing the Watchdog
532
Quick Test
532
Byte Test
532
Backup Reset Generator
534
Generated Resets and Interrupts
534
Memory Map and Register Definition
535
Watchdog Status and Control Register High (WDOG_STCTRLH)
536
Watchdog Status and Control Register Low (WDOG_STCTRLL)
538
Watchdog Time-Out Value Register High (WDOG_TOVALH)
538
Watchdog Time-Out Value Register Low (WDOG_TOVALL)
539
Watchdog Window Register High (WDOG_WINH)
539
Watchdog Window Register Low (WDOG_WINL)
540
Watchdog Refresh Register (WDOG_REFRESH)
540
Watchdog Unlock Register (WDOG_UNLOCK)
540
Watchdog Timer Output Register High (WDOG_TMROUTH)
541
Watchdog Timer Output Register Low (WDOG_TMROUTL)
541
Watchdog Reset Count Register (WDOG_RSTCNT)
542
Watchdog Prescaler Register (WDOG_PRESC)
542
Watchdog Operation with 8-Bit Access
542
General Guideline
543
Refresh and Unlock Operations with 8-Bit Access
543
Restrictions on Watchdog Operation
544
Multipurpose Clock Generator (MCG)
547
Introduction
547
Features
547
Modes of Operation
551
External Signal Description
551
Memory Map/Register Definition
551
MCG Control 1 Register (MCG_C1)
552
MCG Control 2 Register (MCG_C2)
553
MCG Control 3 Register (MCG_C3)
554
MCG Control 4 Register (MCG_C4)
555
MCG Control 5 Register (MCG_C5)
556
MCG Control 6 Register (MCG_C6)
558
MCG Status Register (MCG_S)
559
MCG Auto Trim Control Register (MCG_ATC)
561
MCG Auto Trim Compare Value High Register (MCG_ATCVH)
561
MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
562
Functional Description
562
MCG Mode State Diagram
562
Low Power Bit Usage
567
MCG Internal Reference Clocks
567
External Reference Clock
568
MCG Fixed Frequency Clock
568
MCG PLL Clock
569
MCG Auto TRIM (ATM)
569
Initialization / Application Information
570
MCG Module Initialization Sequence
570
Using a 32.768 Khz Reference
572
MCG Mode Switching
573
Oscillator (OSC)
583
Introduction
583
Features and Modes
583
Block Diagram
584
OSC Signal Descriptions
584
External Crystal / Resonator Connections
585
External Clock Connections
586
Memory Map/Register Definitions
587
OSC Memory Map/Register Definition
587
Functional Description
588
OSC Module States
589
OSC Module Modes
590
Counter
592
Reference Clock Pin Requirements
592
Reset
592
Low Power Modes Operation
593
Interrupts
593
RTC Oscillator
595
Introduction
595
Features and Modes
595
Block Diagram
595
RTC Signal Descriptions
596
EXTAL32 - Oscillator Input
596
XTAL32 - Oscillator Output
596
External Crystal Connections
597
Memory Map/Register Descriptions
597
Functional Description
597
Reset Overview
598
Interrupts
598
Flash Memory Controller (FMC)
599
Introduction
599
Overview
599
Features
600
Modes of Operation
600
External Signal Description
600
Memory Map and Register Descriptions
601
Flash Access Protection Register (FMC_PFAPR)
607
Flash Bank 0 Control Register (FMC_PFB0CR)
610
Flash Bank 1 Control Register (FMC_PFB1CR)
613
Cache Tag Storage (Fmc_Tagvdw0Sn)
615
Cache Tag Storage (Fmc_Tagvdw1Sn)
616
Cache Tag Storage (Fmc_Tagvdw2Sn)
617
Cache Tag Storage (Fmc_Tagvdw3Sn)
618
Cache Data Storage (Upper Word) (Fmc_Dataw0Snu)
619
Flash Program and Erase
661
FTFL Command Operations
661
Margin Read Commands
670
FTFL Command Description
671
Security
699
Reset Sequence
701
External Bus Interface (Flexbus)
703
Introduction
703
Overview
703
Features
704
Modes of Operation
704
Signal Descriptions
704
Address and Data Buses (Fb_An, Fb_Dn, Fb_Adn)
705
Chip Selects (FB_CS[5 :0])
705
Byte Enables (FB_BE_31_24, FB_BE_23_16, FB_BE_15_8, FB_BE_7_0)
706
Output Enable (FB_OE)
706
Read/Write (FB_R/W)
706
Transfer Start/Address Latch Enable (FB_TS/FB_ALE)
706
Transfer Size (FB_TSIZ[1:0])
707
Transfer Burst (FB_TBST)
707
Transfer Acknowledge (FB_TA)
708
Memory Map/Register Definition
708
Chip Select Address Register (Fb_Csarn)
710
Chip Select Mask Register (Fb_Csmrn)
711
Chip Select Control Register (Fb_Cscrn)
712
Chip Select Port Multiplexing Control Register (FB_CSPMCR)
715
Functional Description
716
Chip-Select Operation
716
Data Transfer Operation
718
Data Byte Alignment and Physical Connections
718
Address/Data Bus Multiplexing
719
Bus Cycle Execution
720
Flexbus Timing Examples
722
Burst Cycles
740
Extended Transfer Start/Address Latch Enable
749
Bus Errors
749
Initialization/Application Information
750
Initializing a Chip Select
750
Reconfiguring a Chip Select
750
Overview
751
Introduction
751
Features
752
Modes of Operation
752
External Signal Description
753
Ezport Clock (EZP_CK)
753
Ezport Chip Select (EZP_CS)
753
Ezport Serial Data in (EZP_D)
754
Ezport Serial Data out (EZP_Q)
754
Command Definition
754
Command Descriptions
755
Flash Memory Map for Ezport Access
761

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NXP Semiconductors MK53DX256ZCLQ10 Manuals

NXP Semiconductors MK53DX256ZCLQ10 Reference Manual (1823 pages)

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