ARTERY AT32F403ARGT7 Manuals
Manuals and User Guides for ARTERY AT32F403ARGT7. We have 1 ARTERY AT32F403ARGT7 manual available for free PDF download: Reference Manual
ARTERY AT32F403ARGT7 Reference Manual (490 pages)
Brand: ARTERY
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Category: Computer Hardware
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Size: 6 MB
Table of Contents
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ARM Cortex37
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Bit Band38
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Reset43
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Flash Memory47
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SRAM Memory49
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Introduction52
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Por/Lvr52
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Power Domain53
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Clock58
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System Clock59
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Interrupts60
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Reset60
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System Reset60
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Unlock/Lock82
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Unlock/Lock86
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Introduction100
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GPIO Structure100
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GPIO Registers102
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Introduction105
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IOMUX Structure105
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IOMUX Registers108
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(Iomux_Exintc1)111
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(Iomux_Exintc2)112
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(Iomux_Exintc3)113
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EXINT Registers122
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Introduction124
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Main Features124
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Arbiter125
-
Errors127
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Interrupts127
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DMA Registers129
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CRC Introduction137
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CRC Registers137
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C Interface139
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I 2 C Interface140
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Smbus151
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C Debug Mode153
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I 2 C Registers154
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Mode Selector163
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Introduction163
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Introduction165
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Configuration165
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Transmitter166
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Receiver166
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I/O Pin Control169
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USART Registers169
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SPI Introduction175
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SPI Description175
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Crc178
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DMA Transfer179
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Transmitter180
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Receiver180
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Interrupt181
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IO Pin Control181
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Precautions182
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S Introduction182
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DMA Transfer188
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Interrupts189
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IO Pin Control189
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SPI Registers190
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Mode)190
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Mode)193
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Timer195
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Count Clock196
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Counting Mode196
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Debug Mode197
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Count Clock200
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Counting Mode202
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Debug Mode211
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Tmrx Registers211
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Count Clock224
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Counting Mode225
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Debug Mode229
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Count Clock242
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Counting Mode244
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Debug Mode253
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Debug Mode270
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WWDT Registers270
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WDT Introduction272
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Debug Mode273
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WDT Registers273
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RTC Introduction275
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RTC Structure275
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RTC Interrupts277
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RTC Registers278
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BPR Introduction281
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BPR Registers281
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ADC Introduction285
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ADC Structure285
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Trigger288
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Sequence Mode290
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Repetition Mode291
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Partition Mode291
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Data Management292
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Data Alignment292
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Data Read292
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Voltage Monitor292
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Data Management293
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ADC Registers296
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DAC Introduction308
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Design Tips308
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Trigger Events309
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DAC Registers311
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(Dac_ Ddth12R)315
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Can316
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CAN Introduction316
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Baud Rate316
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Operating Modes321
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Test Modes321
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Error Management326
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CAN Registers327
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XMC Introduction342
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XMC Architecture343
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Block Diagram343
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Address Mapping344
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Nor/Psram345
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Operation Mode345
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Access Mode346
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Multiplexed Mode359
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Synchronous Mode361
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Nand363
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Operation Mode363
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Access Timings364
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ECC Computation366
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XMC Registers366
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(Xmc_Bk1Ctrl1)367
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(Xmc_Bk1Ctrl4)368
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SDIO Interface375
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Erase379
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Commands382
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Response Formats385
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SDIO Adapter388
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Data BUF392
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SDIO Registers394
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SDIO Response 1397
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USB Buffer405
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SOF Output407
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Suspend/Resume407
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USBFS Interrupts407
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USBFS Registers407
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ACC Introduction413
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Main Features413
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Principle415
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EMAC Structure420
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EMAC Interrupts449
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EMAC Registers450
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(Emac_Mmcrfcecr)479
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(Emac_Ptpssinc)481
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Debug (DEBUG)485
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Debug and Trace485
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I/O Pin Control485
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DEBUG Registers486
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Revision History489
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