Lattice mVision AR0234 Sensor Board
User Guide
6.3. Operating Current Consumption for MIPI Output
Table 6.3. Operating Current Consumption for MIPI Output
Symbol
Parameter
I
_PHY +
DD
I
_DATA +
Digital Operating Current
DD
I
DD
I
IO_PHY +
I/O Digital Operating
DD
I
_IO
Current
DD
I
_PHY + T
Analog Operating Current
AA
AA
I
_PIX
Pixel Supply Current
AA
Notes:
1.
(V
= V
_PIX = V
_IO = 2.8 V; V
AA
AA
DD
C
= 10 pF)
LOAD
2.
Values in
Table 6.3
are subject to change.
3.
The following supply rails can be connected together:
a.
V
, V
_PHY, and V
DD
DD
DD
b.
V
_IO and V
IO_PHY
DD
DD
c.
V
, V
_PHY, and V
AA
AA
AA
6.4. Standby Current Consumption
Table 6.4. Standby Current Consumption
Definition
Apply XSHUTDOWN (Clock Off)
Apply XSHUTDOWN (Clock On)
Soft Standby (Clock Off, Driven Low)
Soft Standby (Clock On, EXTCLK = 27 MHz)
Notes:
1.
(Analog = V
+ V
_PIX + V
AA
AA
2.
Values in
Table 6.4
are subject to change.
6.5. Two-Wire Serial Bus Timing Parameters
Unless otherwise stated, the following specifications apply to the following conditions:
V
= V
_PHY = V
_DATA = 1.2 V +/-0.06;
DD
DD
DD
V
_IO = V
= V
_PIX = 2.8 V +/-0.3 V; V
DD
AA
AA
T
= −40 °C to + 105 °C;
A
Output Load = 10 pF;
PIXCLK Frequency = 90 MHz;
MIPI off
The electrical characteristics of the two−wire serial register interface (S
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
Condition
MIPI, Streaming, Full Resolution 120 fps
MIPI, Streaming, Full Resolution 120 fps
MIPI, Streaming, Full Resolution 120 fps
MIPI, Streaming, Full Resolution 120 fps
= V
_PHY = 1.2 V; V
DD
DD
DDIO
_DATA
_PIX
Condition
Analog, 2.8 V
Digital, 1.8 V
Analog, 2.8 V
Digital, 1.8 V
Analog, 2.8 V
Digital, 1.8 V
Analog, 2.8 V
Digital, 1.8 V
_PHY; Digital = V
V
_IO + V
AA
DD +
DD
_PHY = 1.8 V +/-0.1 V
DDIO
Min
TBD
TBD
TBD
TBD
_PHY = 1.8 V; PLL Enabled and PIXCLK = 90 MHz; T
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
_PHY + V
_PHY + V
_DATA; T
DD
DDIO
DD
, S
) are shown in
CLK
DATA
Typ
Max
147
TBD
8
—
TBD
55
6
TBD
= 25 °C;
A
Typ
Max
Unit
10
TBD
µA
40
TBD
µA
25
TBD
µA
55
TBD
µA
15
TBD
µA
270
TBD
µA
70
TBD
µA
2600
TBD
µA
= 25 °C)
A
Figure 6.1
and
Table
FPGA-UG-02124-1.1
Unit
mA
mA
mA
mA
6.5.