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Lattice Semiconductor LatticeMico GPIO Manual

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Features
LatticeMico GPIO
The LatticeMico GPIO is a general-purpose input/output core that provides a
memory-mapped interface between a WISHBONE slave port and general-
purpose I/O ports. The I/O ports can connect to either on-chip or off-chip logic.
This document describes the 3.5 version of the LatticeMico GPIO.
The LatticeMico GPIO includes the following features:
WISHBONE B.3 interface
WISHBONE data base size configurable to 8 or 32 bits wide
Four transfer port types: tristate, input, output, independent input/output
Interrupt request (IRQ) generation on level-sensitive or edge-sensitive
input
Hardware interrupt mask register
Figure 1 shows the deployment of the LatticeMico GPIO within the FPGA and
its input and output ports.
For additional details about the WISHBONE bus, refer to the LatticeMico8
Processor Reference Manual or the LatticeMico32 Processor Reference
Manual.
Copyright © January 2014 Lattice Semiconductor Corporation.

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Summary of Contents for Lattice Semiconductor LatticeMico GPIO

  • Page 1 Hardware interrupt mask register  Figure 1 shows the deployment of the LatticeMico GPIO within the FPGA and its input and output ports. For additional details about the WISHBONE bus, refer to the LatticeMico8 Processor Reference Manual or the LatticeMico32 Processor Reference Manual.

  • Page 2: Functional Description

    Functional Description The LatticeMico GPIO creates an interface between the LatticeMico RISC processor and a simple bit-level control interface. The control bits can be connected to either internal or external logic. Control of the input or output pins is managed using four memory-mapped registers. The memory-mapped registers control reading and writing the input/output bits, tristating the I/O bits, interrupt masking, and an “edge event”...

  • Page 3: Tristate Control

    Figure 2 is an internal block diagram of the GPIO showing its bidirectional ports. It shows how the PIO_TRI register (see Table 4) determines whether the PIO_DATA register is used to transfer data in or out. Figure 2: LatticeMico GPIO Core Usage with Bidirectional Ports Read Data...
  • Page 4 Output Port Type For the output port type, the PIO ports can drive output only (PIO_OUT). Input Port Type For the input port type, the PIO ports can capture input only (PIO_IN). LatticeMico GPIO...
  • Page 5 GPIO defines which I/Os can cause an interrupt request. When the IRQ mode is turned off, the IRQ_MASK register does not exist. Figure 3 shows a bidirectional LatticeMico GPIO similar to that shown in Figure 2 but with the ability to generate interrupt requests. The GPIO in Figure 3 can generate interrupt requests as a signal switches from 0 to 1 or 1 to 0 (edge capture).
  • Page 6 Table 2 describes the parameters that appear in the HDL. I/O Ports Table 3 describes the input and output ports of the LatticeMico GPIO. User Impact of Initial State For the output port, the initial state is low after reset.
  • Page 7 Configuration Figure 4: LatticeMico GPIO Usage with IRQ (Level Triggered) Read Data PIO_DATA Write Address PIO_IO [n - 1:0] Control Direction PIO_TRI Interrupt Level mask detection Table 1: GPIO UI Parameters Dialog Box Option Description Allowable Values Default Value Instance Name Specifies the name of the GPIO instance.
  • Page 8 OUTPUT_PORTS_ONLY A value of 1 defines the transfer mode for PIO 0 | 1 ports as output only. TRISTATE_PORTS A value of 1 defines the transfer mode for PIO 0 | 1 ports as tristate only. LatticeMico GPIO...
  • Page 9 GPIO_DAT_I — Data input array, valid for a write request GPIO_LOCK_I High Lock input. If asserted, the current cycle becomes uninterruptible. GPIO_SEL_I High Select input array, which indicates where the valid data is expected on a data bus. LatticeMico GPIO...

  • Page 10: Register Definitions

    Interrupt request outputs. The GPIO can be configured to generate an IRQ on certain input conditions. Register Definitions The LatticeMico GPIO includes the registers shown in Table 4. See “Software Usage Examples” on page 21 for examples that show how to access these registers in order to access the programmable I/O pins.
  • Page 11 Setting a bit to 0 disables interrupt generation for the corresponding PIO_IN/IO pin. A change from 0 to 1 clears the corresponding EDGE_CAPTURE register. Example: Writing a word 0xFF000000 to address offset 0 will enable interrupt generation for PIO_IN/IO[7:0] and disable it for PIO_IN/IO[31:8] LatticeMico GPIO...

  • Page 12: Timing Diagrams

    The timing diagrams featured in Figure 5 through Figure 9 show the timing of the GPIO’s WISHBONE and external signals. Figure 5 shows how the GPIO’s master ports update the data in the internal register. Figure 5: WISHBONE Master Writes Data in the Internal Register LatticeMico GPIO...
  • Page 13 Figure 7: IRQ Generation (Level) Figure 8 shows how the GPIO generates interrupt requests when the PIO_DATA signal transitions from low to high. After an edge is detected, the Edge_Capture bit is held at a 1 until cleared in the IRQ_MASK register. LatticeMico GPIO...
  • Page 14 Figure 8: IRQ Generation (Rising Edge) Figure 9 shows how the GPIO generates interrupt requests when the PIO_DATA signal transitions from high to low. Figure 9: IRQ Generation (Falling Edge) EBR Resource Utilization The LatticeMico GPIO uses no EBRs. LatticeMico GPIO...

  • Page 15: Usage Model

    In a big-endian architecture, the most-significant byte of a multi-byte object is stored at the lowest address, and the least- significant byte of that object is stored at the highest address. LatticeMico GPIO...
  • Page 16 Table 4 on page 10. This structure, which is defined in the MicoGPIO.h header file, enables you to directly access the GPIO registers, if desired. It is used internally by the device driver for manipulating the GPIO. LatticeMico GPIO...

  • Page 17: Device Driver

    MSB managed build process, which extracts the GPIO component-specific information from the platform definition file. The members should not be manipulated directly, because this structure is for exclusive use by the device driver. LatticeMico GPIO...
  • Page 18 This value represents the input width if the GPIO is configured for input and output mode. output_width unsigned int This value represents the output width if the GPIO is configured for input and output mode. LatticeMico GPIO...
  • Page 19 // write the "shadow" values out to the I/O pins pGPIO->gpioData = gpioState.gpioData; // do a read of the "shadow" value and then clear the lsb gpioState->gpioData &= 0xFE; // write the new value to the I/O pins pGPIO->gpioData = pGpioState->gpioData; // ... LatticeMico GPIO...
  • Page 20 /* writes irq-mask register */ #define MICO_GPIO_WRITE_IRQ_MASK(X,Y) ((volatile MicoGPIO_t *)((X)->base))->irqMask = (Y) /* reads edge-capture register */ #define MICO_GPIO_READ_EDGE_CAPTURE(X,Y) (Y) = ((volatile MicoGPIO_t *)((X)->base))->edgeCapture /* writes to the edge-capture register */ #define MICO_GPIO_WRITE_EDGE_CAPTURE(X,Y) ((volatile MicoGPIO_t *)((X)->base))->edgeCapture = (Y) LatticeMico GPIO...
  • Page 21 Figure 17: Locating a GPIO and Accessing Its Data Register /* Fetch GPIO instance named "LED" */ unsigned int iValue; MicoGPIOCtx_t *leds = (MicoGPIOCtx_t *)MicoGetDevice("led"); if (leds == 0) { /* failed to find a component named "leds" */ return(-1); LatticeMico GPIO...
  • Page 22 The members should not be manipulated directly, because this structure is for exclusive use by the device driver. Figure 18 shows the GPIO device context structure. Figure 10 describes the parameters of the GPIO device context structure shown in Figure 18. LatticeMico GPIO...
  • Page 23 This value is set to 0 if the GPIO is not configured to generate interrupts. Otherwise, the value is 1. Functions Since the GPIO is a general-purpose device and does not fit a well-defined usage scenario, there are no predefined functions. However, there are LatticeMico GPIO...
  • Page 24 (__builtin_export((char)(Y), (size_t)(X+GPIO_DATA_OFFSET+0))) #define MICO_GPIO_WRITE_DATA_BYTE1(X, Y) \ (__builtin_export((char)(Y), (size_t)(X+GPIO_DATA_OFFSET+1))) #define MICO_GPIO_WRITE_DATA_BYTE2(X, Y) \ (__builtin_export((char)(Y), (size_t)(X+GPIO_DATA_OFFSET+2))) #define MICO_GPIO_WRITE_DATA_BYTE3(X, Y) \ (__builtin_export((char)(Y), (size_t)(X+GPIO_DATA_OFFSET+3))) /* Macros for accessing each byte of the Tristate Register */ #define MICO_GPIO_READ_TRISTATE_BYTE0(X, Y) \ (Y) = (__builtin_import((size_t)(X+GPIO_TRISTATE_OFFSET+0))) LatticeMico GPIO...
  • Page 25 #define MICO_GPIO_READ_IRQ_MASK_BYTE2(X, Y) \ (Y) = (__builtin_import((size_t)(X+GPIO_IRQ_MASK_OFFSET+2))) #define MICO_GPIO_READ_IRQ_MASK_BYTE3(X, Y) \ (Y) = (__builtin_import((size_t)(X+GPIO_IRQ_MASK_OFFSET+3))) /* Macros for writing each byte of the IRQ Mask Register */ #define MICO_GPIO_WRITE_IRQ_MASK_BYTE0(X, Y) \ (__builtin_export((char)(Y), (size_t)(X+GPIO_IRQ_MASK_OFFSET+0))) #define MICO_GPIO_WRITE_IRQ_MASK_BYTE1(X, Y) \ (__builtin_export((char)(Y), (size_t)(X+GPIO_IRQ_MASK_OFFSET+1))) LatticeMico GPIO...
  • Page 26 Software Usage Examples This section provides code example that demonstrate how to locate a GPIO device that is instantiated in the platform and how to directly access the data register using the macros provided in MicoGPIO.h header file. LatticeMico GPIO...
  • Page 27 Added LatticeMico8 software support. Fixed issues with synthesis when component is configured for both input and output ports and the widths of each are different. Updated document with new corporate logo. Improved modules naming system to support component scanning function. LatticeMico GPIO...
  • Page 28 The Simple Machine for Complex Design, TraceID, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP, Bringing the Best Together, and More of the Best are service marks of Lattice Semiconductor Corporation.

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