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Lattice Semiconductor sysCLOCK ECP5 Usage Manual

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November 2015
Introduction
This usage guide describes the clock resources available in the ECP5
Details are provided for primary clocks, edge clocks, PLLs, the internal oscillator, and clocking elements such as
clock dividers, clock multiplexers, and clock stop blocks available in the ECP5 and ECP5-5G device.
The number of PLLs, Edge clocks, and Clock dividers for each device is listed in Table 1.
Table 1. Number of PLLs, Edge Clocks, and Clock Dividers
Parameter
Number of PLLs
Number of Edge Clocks
Number of Clock Dividers
Number of PCS Clock Dividers
Number of DDRDLLs
1. LFE5U devices do not have PCS Clock Dividers.
It is very important to note that the user needs to validate their pinout so that correct pin placement is used. The
®
Lattice Diamond
tools should be used to validate the pinout while designing the printed circuit board.
Clock/Control Distribution Network
ECP5 and ECP5-5G devices provide global clock distribution in the form of 16 global primary clocks. These Pri-
mary clocks can be divided into 16 clocks per each of the four quadrants; however there is a maximum of 60 unique
clock input sources. The ECP5 and ECP5-5G primary clocking structure is enhanced as it features more Edge
clock resources, more low-skew Primary clock resources and removes the Secondary clock resources.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Description
General purpose PLLs.
Edge Clocks for high speed applica-
tions.
Edge Clock Dividers for DDR applica-
tions.
1
Clock dividers for domain crossing appli-
cations.
DDRDLL used to DDR memory and
High Speed IO interfaces
TM
and ECP5-5G
1
LFE5-85
4
8
4
2
4
1
Technical Note TN1263
TM
device architecture.
LFE5-45
LFE5-25
4
2
8
8
4
4
2
1
4
2
TN1263_1.1

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Summary of Contents for Lattice Semiconductor sysCLOCK ECP5

  • Page 1 Primary clock resources and removes the Secondary clock resources. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 2: Appendix A. Primary Clock Sources And Distribution Section

    ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide ECP5 and ECP5-5G Top-Level View A top level view of the major clocking resources for the ECP5 and ECP5-5G devices is shown in Figure 1. Figure 1. ECP5 and ECP5-5G Clocking Structure (LFE5-85) Bank 0 Bank 1 GPLL...
  • Page 3 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Overview of Other Clocking Elements Edge Clock Dividers (CLKDIVF) Clock dividers are provided to create the divided down clocks used with the I/O Mux/DeMux gearing logic (SCLK inputs to the DDR) and drives to the Primary Clock routing to the fabric. There are four clock dividers on the ECP5 and ECP5-5G device.
  • Page 4 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide sysCLOCK PLL Overview The sysCLOCK PLLs can be used in a variety of clock management applications such as clock injection removal, clock phase adjustment, clock timing adjustment, and frequency synthesis (multiplication and division of a clock). The ECP5 and ECP5-5G Clarity Designer PLL GUI shows important timing parameters such as the VCO rate and the PLL loop bandwidth.

  • Page 5: Clock Phase Adjustment

    ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide PLL Features Dedicated PLL Inputs The PLLs have dedicated PLL input pins that are not Primary Clock input pins. Each of the Top Left and Right cor- ner PLLs have two pairs of dedicated PLL input pins, one from the Left/Right side bank and the other from the Top bank.

  • Page 6: Frequency Synthesis

    ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Frequency Synthesis The PLL can be used to multiply up or divide down an input clock. Additional Features In addition to the major features, the PLL has several other options that can be used in conjunction with the major modes.
  • Page 7 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 5. Primary Clock Routing Architecture Primary Clock Sources Into the Mid-Mux Quadrant TL Quadrant TR Primary Clock Routing to Fabric Resources in Primary Clock Routing to Fabric Resources in TL Quadrant of the FPGA TR Quadrant of the FPGA Primary Clock Primary Clock...
  • Page 8 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide There is one PCSCLKDIV per SERDES Channel on the bottom of the device where the SERDES blocks are located. The clock outputs of the PCSCLKDIV (CDIV1, CDIVX) are delay and phase matched to each other and has a run-time selectable divider value.
  • Page 9 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide An example design is shown in Figure 8. It is a flip-flop based clock domain crossing circuit between the CDIV1 and the CDIVX = 2 clock outputs of the PCSCLKDIV. In this example an IP core is using the PCSCLKDIV to change the operating frequency and bus width for a PCS (SERDES) application.
  • Page 10 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide PCSCLKDIV Usage in VHDL Component Instantiation Library lattice; use lattice.components.all; Component and Attribute Declaration component PCSCLKDIV Generic (GSR : string); Port (RST : in STD_LOGIC; CLKI : in STD_LOGIC; : in STD_LOGIC_VECTOR(2 downto 0);...
  • Page 11 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Dynamic Clock Select (DCSC) The ECP5 and ECP5-5G device has two dynamic clock select (DCS) blocks that can drive to any or all the quad- rants. The inputs to the DCS block come from all the output of MIDMUXs and local routing that is located at the center of the PLC array core.
  • Page 12 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide DCS Timing Diagrams Figure 10 shows timing diagrams to show the operation of the DCS in Glitchless mode in conjunction with the DCS- MODE attribute. Figure 10. Timing Diagrams by “DCSMODE” Attribute Setting, Glitchless Operation (MODESEL=’0’) DCSMODE = “POS”...
  • Page 13 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 11. DCS Operation, Non-Glitchless Operation (MODESEL=’1’) SEL[3:0] “0001” “0010” “0001” CLK0 CLK1 DCSOUT DCSC Component Definition The DCSC component can be instantiated in the source code of a design as defined in this section. Figure 12.
  • Page 14 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide DCSMODE Attribute Table 5 provides the behavior of the DCS output based on the setting of the DCSMODE attribute when the pin MODESEL =’0’. The MODESEL pin is dynamic and can toggle during operation. Table 5 is only valid when MODE- SEL =’0’.
  • Page 15 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide DCSC Usage in Verilog Component and Attribute Declaration module DCSC(CLK0,CLK1,CLK2,CLK3,SEL,MODESEL,DCSOUT); input CLK0; input CLK1; input [1:0] SEL; input MODESEL; output DCSOUT; endmodule DCSC Instantiation defparam DCSInst0.DCSMODE = “POS”; DCSC DCSInst0 ( .CLK0 (CLK0) ,.CLK1...
  • Page 16 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide DCCA Component Definition The DCCA component can be instantiated in the source code of a design as defined in this section. Figure 14 and Table 6 show the DCCA definitions. Figure 14. DCCA Component Symbol CLKI CLKO DCCA...
  • Page 17 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Internal Oscillator (OSCG) The OSCG element performs multiple functions on the ECP5 and ECP5-5G device. It is used for configuration, SED, as well as optionally in user mode. In user mode, the OSCG element has the following features: •...
  • Page 18 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide OSCG Usage in Verilog Component and Attribute Declaration module OSCG (OSC); output OSC; endmodule OSCG Instantiation OSCG I1 (.OSC(OSC)) Edge Clocks Each ECP5 and ECP5-5G device I/O bank has four ECLK resources. These clocks, which have low injection time and skew, are used to clock I/O registers.
  • Page 19 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Edge Clock Dividers (CLKDIVF) There are four edge clock dividers available in the ECP5 and ECP5-5G device, two per side of the device. The clock divider provides a single divided output with available divide values of 2 or 3.5. The inputs to the clock divid- ers are the edge clocks, PLL outputs and Primary Clock Input pins.
  • Page 20 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide CLKDIVF Instantiation attribute DIV : string; attribute DIV of I1 : label is “2.0”; attribute GSR : string; attribute GSR of I1 : label is “DISABLED”; I1: CLKDIVF generic map (DIV =>...
  • Page 21 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide ECLKBRIDGECS Component Definition The ECLKBRIDGECS component must be instantiated in the source code of a design in order to bridge Edge clocks. Figure 18 and Table 11 define the ECLKBRIDGECS. Note that an ECLKSYNCB module has to be always used after the ECLKBRIDGECS instance to be able to con- nect to the ECLK tree.
  • Page 22 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide DCSC Instantiation ECLKBRIDGECS ECSInst0 ( .CLK0 (CLK0) ,.CLK1 (CLK1) ,.SEL (SEL) ,.ECSOUT (ECSOUT)); Edge Clock Synchronization (ECLKSYNCB) ECP5 and ECP5-5G devices have dynamic edge clock synchronization control (ECLKSYNCB) which allows each edge clock to be disabled or enabled glitchlessly from core logic if desired.
  • Page 23 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide ECLKSYNCB Usage in VHDL Component Instantiation Library lattice; use lattice.components.all; Component and Attribute Declaration COMPONENT ECLKSYNCB PORT (ECLKI STD_LOGIC; STOP STD_LOGIC; ECLKO :OUT STD_LOGIC); END COMPONENT; ECLKSYNCB Instantiation I1: ECLKSYNCB port map ( ECLKI =>...
  • Page 24 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide For a very small clock domain, the user can limit the distance of a general routing based (gated) clock to one PLC in distance to the logic it clocks. The user must group this logic (UGROUP) with a BBOX = “1, 1” (see Diamond Help >...
  • Page 25 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 24. PLL Component Instance CLKI CLKOP CLKFB CLKOS CLKOS 2 PHASESEL [1:0] CLKOS 3 PHASEDIR LOCK PHASESTEP INTLOCK PHASELOADREG REFCLK STDBY EHXPLLL CLKINTFB PLLWAKESYNC ENCLKOP ENCLKOS ENCLKOS 2 ENCLKOS 3 Table 13.

  • Page 26: Functional Description

    ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Functional Description Refclk (CLKI) Divider The CLKI divider is used to control the input clock frequency into the PLL block. The valid input frequency range is specified in the device data sheet. Feedback Loop (CLKFB) Divider The CLKFB divider is used to divide the feedback signal, effectively multiplying the output clock.
  • Page 27 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 25. PLL Dedicated Inputs to the PLLREFCS Component for Top Left and Right PLL PLLREFCS Dedicated CLK 0 External PLL Input 0 Primary Clock Inputs PLL 0 PLLCSOUT Edge Clock Inputs CLK 1 CLKI Dedicated...
  • Page 28 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 26. RST Input Timing Diagram Trst Trstrec CLKI CLKOP/OS/ OS2/OS3 Dynamic Clock Enables Each PLL output has a user input signal to dynamically enable / disable its output clock glitchlessly. When the clock enable signal is set to logic ‘0’, the corresponding output clock is held to logic ‘0’.
  • Page 29 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide PHASEDIR Input The PHASEDIR input is used to specify which direction the dynamic phase shift will occur, advanced (leading) or delayed (lagging). When PHASEDIR = 0 then the phase shift will be delayed. When PHASEDIR = 1 then the phase shift will be advanced.
  • Page 30 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide LOCK Output The LOCK output provides information about the status of the PLL. After the device is powered up and the input clock is valid, the PLL will achieve lock within 16 ms. Once lock is achieved, the PLL LOCK signal will be asserted. The LOCK signal can be set in Clarity Designer in either the default “unsticky”...
  • Page 31 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide For Example: PHASESEL[1:0]=2’b00 to select CLKOS for phase shift PHASEDIR =1’b0 for selecting delayed (lagging) phase Assume the output is divided by 2, CLKOS_DIV = 2 The CLKOS_FPHASE is set to 1 The above signals need to be stable for 5 ns before the falling edge of PHASESTEP and the minimum pulse width of PHASESTEP should be four VCO clock cycles.
  • Page 32 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Low Power Features The ECP5 and ECP5-5G PLL contains several features that allow the user to reduce the power usage of a design including Standby mode support and Dynamic clock enable. Dynamic Clock Enable The Dynamic Clock Enable feature allows the user to glitchlessly enable and disable selected output clocks during periods when not used in the design.
  • Page 33 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 30. Clarity Designer Main Window for PLL Module Configuration Tab The configuration window lists all user accessible attributes with default values set. Upon completion, clicking Gen- erate generates the source. PLL Frequency and Phase Configuration Enter the input and output clock frequencies and the software will calculate the divider settings.
  • Page 34 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 31. ECP5 and ECP5-5G PLL Frequency Configuration Tab Table 18. Page 1, PLL Frequency Settings, Clarity Designer GUI Corresponding User Parameters Description Range Default HDL Attribute CLKI Frequency Input 10 – 400 MHz 100 MHz FREQUENCY_PIN _CLKI...
  • Page 35 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Corresponding User Parameters Description Range Default HDL Attribute CLKOP Enable ON / OFF CLKOP_ENABLE Bypass ON / OFF OUTDIVIDER_MU — — Output Divider (read only) CLKOP_DIV Desired Frequency *1 3.125 – 400 MHz 100 MHz FREQUENCY_PIN _CLKOP...
  • Page 36 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 32. ECP5 and ECP5-5G PLL Phase Configuration Tab Table 19. Tab 2, PLL Phase Settings, Clarity Designer GUI Corresponding User Parameters Description Range Default HDL Attribute CLKOP Desired Phase*1 (Based on Fre- 100 MHz CLKOP_CPHASE, quency)
  • Page 37 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 33. ECP5 and ECP5-5G PLL Optional Ports Configuration Tab Table 20. Tab 3, PLL Optional Ports, Clarity Designer GUI Corresponding User Parameters Description Range Default HDL Attribute Enable Clock Select Enables the input clock mux (PLLREFCS ON / OFF component).
  • Page 38 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide For the PLL, Clarity Designer sets attributes in the HDL module that are specific to the data rate selected. Although these attributes can be easily changed, they should only be modified by re-running the GUI so that the perfor- mance of the PLL is maintained.

  • Page 39: Technical Support Assistance

    ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide module PLLREFCS(CLK0, CLK1, SEL, PLLCSOUT); input CLK0, CLK1, SEL; output PLLCSOUT; endmodule; PLLREFCS Instantiation PLLREFCS PLLREFCSInst0 ( .CLK0 (CLK_0) ,.CLK1 (CLK_1) ,.SEL (SELECT) ,.PLLCSOUT (CLK_OUT)); Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport. Revision History Date Version...
  • Page 40 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Appendix A. Primary Clock Sources and Distribution The following figures show the inputs into the Primary Clock Network through the mid-mux into the centermux for each device. There are DCC components at the input of the centermux to allow the user to stop the clock in order to save power.
  • Page 41 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 36. ECP5 and ECP5-5G Primary Clock Sources and Distribution, LFE5UM/LFE5UM5G-45 Devices PLL_TL OP PLL_TR OP PLL_TL OS PLL_TR OS PLL_TL OS2 PLL_TR OS2 PLL_TL OS3 PLL_TR OS3 Mid Mux Quadrant TL Quadrant TR Primary Primary...
  • Page 42 ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Figure 37. ECP5 and ECP5-5G Primary Clock Sources and Distribution, LFE5UM/LFE5UM5G-25 Devices Mid Mux Quadrant TL Quadrant TR Primary Primary OSC output Clocking Clocking ulc_pclkcib0 urc_pclkcib0 ulq_pclkcib1 urq_pclkcib1 ulq_pclkcib0 urq_pclkcib0 urm_pclkcib0 ulm_pclkcib0 PCLK6_0 PCLK2_0...

  • Page 43: Appendix B. Pinout Rules For Clocking In Ecp5 And Ecp5-5G Devices

    ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and Usage Guide Appendix B. Pinout Rules for Clocking in ECP5 and ECP5-5G Devices In the ECP5 and ECP5-5G device, as with all other architectures, there are general rules and guidelines for board designers which are required to be followed. These rules will give the best possible timing and allow for a success- ful design.

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