Power-On Reset And Standby Timing; Power-Up Sequence; Figure 7.1. Power-Up Sequence - Lattice Semiconductor mVision AR0234 User Manual

7. Power-On Reset and Standby Timing

7.1. Power-Up Sequence

The recommended power-up sequence for the AR0234 is shown in
(VAA/VAA_PIX/VAA_PHY, VDDIO, VDDIO_PHY, VDD/VDD_PHY, and VDD_DATA) must have the separation specified
below.

Turn on VAA/VAA_PIX/VAA_PHY power supply.

After 100 µs, turn on VDDIO power supply.

After 100 µs, turn on VDDIO_PHY (1.8 V) power supply.

After 100 µs, turn on VDD/VDD_PHY power supply.

After 100 µs, turn on VDD_DATA power supply.

After the last power supply is stable, enable EXTCLK.

Assert RESET_N for at least 1 ms. The parallel interface is tristated during this time.

Wait for ~150000 EXTCLKs for internal initialization into soft standby where M3ROM and full OTPM upload is
complete.

Set streaming mode (mode_select/stream (R0x301A[2]) = 1) and the internal PLL is enabled (not locked yet).

Wait for 1 ms for PLL lock to complete, and then part goes into streaming mode.
V
AA
V
AA_PIX
t
1
V
AA_PHY
(2.8)
IO
V t
(1.8/2.8)
DD
IO
V
(1.8)
DD_PHY
V
DD
V
DD_PHY
(1.2)
V
(1.2)
DD_DATA
EXTCLK
RESET_BAR
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1
2
t
3
t
4
t
5
t
Hard
x
Reset

Figure 7.1. Power-up Sequence

Lattice mVision AR0234 Sensor Board
Figure 7.1. The available power supplies
t
6
Internal Software
Initialization Standby
User Guide
t
7
PLL Lock Streaming
19