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Lattice Semiconductor CertusPro-NX Usage Manual

Serdes/pcs
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CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
FPGA-TN-02245-0.81
May 2021

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Summary of Contents for Lattice Semiconductor CertusPro-NX

  • Page 1 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note FPGA-TN-02245-0.81 May 2021...
  • Page 2 The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.

  • Page 3: Table Of Contents

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Contents Glossary ....................................11 Introduction ................................14 Features ..................................15 Using This Technical Note ............................16 Standards Supported ..............................17 Architecture Overview ..............................18 Device Architecture ............................18 SerDes/PCS Architecture ........................... 19 PCI Express Architecture ........................... 20 MPCS Architecture ............................
  • Page 4 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Other Design Considerations ..........................106 Simulation of the SerDes/PCS ......................... 106 PMA PLL Filter ..............................106 Reference Clock Source Selection ........................107 Spread Spectrum Clocking Support ......................... 108 Unused Quad/Channel and Power Supply ...................... 108 Electrical Idle ..............................
  • Page 5 Figure 5.5. MPCS Quad Block Diagram ..........................22 Figure 5.6. MPCS Channel Functional Block Diagram ......................23 Figure 5.7. CertusPro-NX 100k Device SerDes Reference Clock Architecture ..............24 Figure 5.8. PCI Express Hard IP Mode ..........................25 Figure 5.9. PIPE Mode ................................. 26 Figure 5.10.
  • Page 6 Table 4.1. Standards Supported by the SerDes/PCS ......................17 Table 5.1. Maximum Number of SerDes/PCS Channels per CertusPro-NX Device ............. 19 Table 5.2. Maximum Number of PCI Express Blocks per CertusPro-NX Device ..............19 Table 5.3. Block Usage for the Corresponding SerDes/PCS Mode ..................20 Table 5.4.
  • Page 7 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table 6.4. Tx FIFO Usage ..............................54 Table 6.5. Disparity Combinations ............................55 Table 6.6. Example Settings for XAUI and GigE ........................58 Table 6.7. PMA Only Mode Data Bus ..........................69 Table 6.8. Channel Alignment within One Quad ........................ 70 Table 6.9.
  • Page 8 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 21. PRBS Error Counter Register [reg65] ......................129 Table A. 22. PHY Reset Override Register [reg66] ......................129 Table A. 23. PHY Power Override Register [reg67] ......................129 Table A. 24. Transmit PLL Current Charge Pump [reg69] ....................129 Table A.
  • Page 9 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 75. Secondary Lane Alignment Pattern Byte 1 [reg58] ..................143 Table A. 76. Secondary Lane Alignment Pattern Byte 2 [reg59] ..................143 Table A. 77. Secondary Lane Alignment Pattern Byte 3 [reg5a] ..................143 Table A.
  • Page 10 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 129. User Defined BIST Constant 1 Byte_0 [rege3] .................... 153 Table A. 130. User Defined BIST Constant 1 Byte_1 [rege4] .................... 153 Table A. 131. User Defined BIST Constant 1 MSByte [rege5] ................... 153 Table A.

  • Page 11: Glossary

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Glossary A list of vocabulary used in this document. Vocabulary Definition Alternating Current Auto Negotiation ASIC Application Specific Integrated Circuit Bit Error Ratio BIST Built In Self-Test Clock and Data Recovery Consumer Electronic...
  • Page 12 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Vocabulary Definition Interface JIIA Japan Industrial Imaging Association JTAG Joint Test Action Group A low power state inside PCIe LTSSM Low Frequency LMMI Lattice Memory Mapped Interface Loss of Signal LSByte/LSB Last Significant Byte...
  • Page 13 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Vocabulary Definition TxDP Transmitter Data Positive pin TxDN Transmitter Data Negative pin Unit Interval Universal Serial Bus USB3 USB SuperSpeed VC0_RX Virtual Channel 0 Receiver VC0_TX Virtual Channel 0 Transmitter VESA Video Electronics Standards Association...

  • Page 14: Introduction

    SGMII, QSGMII, XAUI, SLVS-EC, and CoaXPress protocols. There are two kinds of Physical Coding Sublayer logic inside the CertusPro-NX device: one is for PCI Express only, the other is Multi-Protocol Physical Coding Sublayer (MPCS) for protocols other than PCI Express.

  • Page 15: Features

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Features  Single Channel MPCS Functionalities From 625 Mb/s up to 10.3125 Gb/s per channel Word alignment and link synchronization FSM Supports DisplayPort, SLVS-EC, CoaXPress, and Ethernet 1000BASE-X/SGMII/XAUI/QSGMII protocols Supports popular 8B/10B PCS-based protocols...

  • Page 16: Using This Technical Note

    Using This Technical Note This technical note provides a thorough description of the complete functionality of the embedded SerDes and associated PCS logic, including the description of:  Architecture of the CertusPro-NX SerDes/PCS module and interface  SerDes/PCS function ...

  • Page 17: Standards Supported

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Standards Supported The supported standards are listed in Table 4.1. Table 4.1. Standards Supported by the SerDes/PCS System Reference Number of Link Standard Data Rate (Mb/s) FPGA Clock (MHz) Encoding Style Clock (MHz)

  • Page 18: Architecture Overview

    Technical Note Architecture Overview Device Architecture The SerDes/PCS block is arranged in quads containing logic for four full-duplex data channels. Figure 5.1 shows the arrangement of SerDes/PCS Quads on the CertusPro-NX 100k device. Configuration Large Large Large Large SERDES/PCS X4...

  • Page 19: Serdes/Pcs Architecture

    PCI Express, while the Multi-Protocol PCS (MPCS) is designed for other protocols. CertusPro-NX device also integrates one PCI Express Link Layer Quad, which contains one PCIe ×1 block and one PCIe ×4 block. The PCIe ×4 PCI Express Link Layer block can be configured as ×1, ×2 or ×4 mode. The PCI Express Link Layer block, PCI Express PCS channels, and PMA channels constitute the complete PCI Express Hard IP block.

  • Page 20: Pci Express Architecture

    PCI Express Architecture The CertusPro-NX PCI Express Link Layer block is a hard IP, which supports PCI Express Gen1, Gen2, and Gen3, and is compatible with PCI-SIG PCI Express Base Spec version 3.1a. The PCI Express Link Layer Block implements PHY Layer adaption, Data Link Layer, and Transaction Layer.

  • Page 21: Figure 5.3. Pci Express Hard Ip Architecture

    Lane 0 and Lane 3 are used for ×1. Figure 5.4 shows the PCI Express Link Layer block functional diagram. For more detailed information on CertusPro-NX PCI Express features, function descriptions, and IP usage, refer to CertusPro-NX PCI Express Hardened IP Core User Guide (FPGA-IPUG-XXXXX). FPGA-TN-02245-0.81 ©...

  • Page 22: Mpcs Architecture

    Figure 5.4. PCI Express Link Layer Functional Diagram MPCS Architecture CertusPro-NX Multi-Protocol PCS is designed for popular serial protocols other than PCI Express, such as Ethernet SGMII, XAUI, QSGMII, 10GBASE-R, SLVS-EC, CoaXpress, and DP/eDP. MPCS can be configured as Generic 8B/10B mode,...

  • Page 23: Figure 5.6. Mpcs Channel Functional Block Diagram

    Since each Quad has its own reference clock, different Quads can support different standards on the same chip. This feature makes the CertusPro-NX family ideal for bridging between different standards. MPCS Quads are not dedicated solely to industry standard protocols. Each Quad and each channel within a Quad can be programmed for many user-defined data manipulation modes.

  • Page 24: Reference Clock Architecture

    SDQx_REFCLKP/SDQx_REFCLKN, or from the FPGA internally. Figure 5.7 shows CertusPro-NX 100k device SerDes/PCS reference clock architecture. The Clock Tree block is designed for balancing the skew between different Quads based on one reference clock source, and the skew between different clock sources.

  • Page 25: Multi-Protocol Design Consideration

    Table 5.6 lists the support of mixed protocols within a CertusPro-NX SerDes/PCS quad. The reference clock must be without spread spectrum when PCI Express and other protocols share the same SerDes/PCS quad. Table 5.6. CertusPro-NX Mixed Protocols within a Quad...

  • Page 26: Figure 5.9. Pipe Mode

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note FPGA Core LMMI MPCS EPCS LMM I PIPE PCI Express Link Layer (x1 + x4) MPCS x4 PCI Express PCS PMA Controller PMA (SERDES) PMA (SERDES) PMA (SERDES) PMA (SERDES) Channel 0 Channel 3...

  • Page 27: Detailed Interface Descriptions

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note FPGA Core LMMI UCFG LMMI MPCS EPCS PCI Express Link Layer (x1 + x4) MPCS x4 PCI Express PCS PMA Controller PMA (SERDES) PMA (SERDES) PMA (SERDES) PMA (SERDES) Channel 0 Channel 3...
  • Page 28 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description Tx/Rx FIFO Signals mpcs_tx_ch_din_i 80*NL For the signal mapping of this port, refer to Table 5.12. mpcs_tx_fifo_st_o 4*NL For the signal mapping of this port, refer to Table 5.12.
  • Page 29 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description switch back to the process of frequency lock acquisition. mpcs_fomreq_i This signal is used to request a Figure of Merit (FOM) evaluation. mpcs_fomack_o This signal is used to handshake the FOM evaluation request in MPCS mode.

  • Page 30: Table 5.8. Epcs Interface

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table 5.8. EPCS Interface Port Name Width Description Clock and Reset Signals epcs_rx_usr_clk_i User interface Rx clock input. epcs_tx_usr_clk_i User interface Tx clock input. epcs_tx_pcs_rstn_i Active low signal used to reset the Tx path of MPCS module.

  • Page 31: Table 5.9. Pipe Interface

    NL means the number of lanes. For the usage about Hardened PCI Express IP and descriptions about TLP interface and UCFG interface, refer to CertusPro-NX PCI Express Hardened IP Core User Guide (FPGA-IPUG-XXXXX).
  • Page 32 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description 2’b00 – Gen1 pipe_powerdown_i 2*NL Powerdown. This is a per-lane signal. pipe_powerdown_i[1:0] = power state driving by the PCI-Express controller: 2’b11 – P2 2’b10 – P1 2’b01 – P0s 2’b00 –...
  • Page 33 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description sync header bits of the 130-bit block. This signal is only valid when both pipe_rxdatavalid_o and pipe_rx_start_block_o are asserted. This signal is a per-lane signal which is generated by the PHY macro for the PCI-Express controller.
  • Page 34 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description which can be enabled to properly lock the CDR and reach a valid state of receiver adaptation. pipe_linkevalchange_o 6*NL Rx equalization link evaluation change. This signal is a per-lane...
  • Page 35 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description for performing the first receiver equalization immediately after entering Gen3 data rate in order to achieve 10 bit error ratio. This preset hint is used by the PHY as an initial value for CTLE...
  • Page 36 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description pipe_tx_elec_idle_LL_i PIPE Tx electrical idle. 1’b1 – Idle. 1’b0 – Active. pipe_block_align_control_LL_i PIPE block align control. 1’b1 – Allows the PHY to align on EIEOS in Gen3 data rate.

  • Page 37: Table 5.10. Lmmi Interface

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description 1’b1 – Data is valid. 1’b0 – Data is invalid. De-asserted only to compensate for 128b130b encoding. pipe_rx_start_block_LL_o PIPE Rx start block. 1’b1 – Start of the block. 1’b0 – Any occurrence other than the start of the block.

  • Page 38: Table 5.11. Other Signals

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Other Signals Table 5.11 shows signals other than MPCS, EPCS, PIPE and LMMI interfaces per quad. NL means the number of lanes. For detailed descriptions about Quad-to-Quad signals, refer to the Clocks and Reset section.

  • Page 39: Table 5.12. Data Bus Sharing And Mapping

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Port Name Width Description the PMA control logic which now controls the PMA hard macro. The PMA hard macro is thus disconnected from the PMA control logic: This signal is used for two purposes: Select the multiplexer between ACJTAG controller and functional logic at the PMA interface directly.
  • Page 40 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note MPCS Mode MPCS Mode MPCS Module Port EPCS Mode Protocol != “10GE” Protocol == “10GE” this signal indicates the forced running disparity: 1: force positive running disparity. 0: force negative running disparity. If not in “force running disparity”...
  • Page 41 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note MPCS Mode MPCS Mode MPCS Module Port EPCS Mode Protocol != “10GE” Protocol == “10GE” through encoder, scrambler and gear box). — — — mpcs_tx_ch_din_i[78:73]/ epcs_txdata_i[78:73] — tx_fifo_wr — mpcs_tx_ch_din_i[79]/ epcs_txdata_i[79] 1: write 64-bit data and 8-bit control to TX FIFO.
  • Page 42 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note MPCS Mode MPCS Mode MPCS Module Port EPCS Mode Protocol != “10GE” Protocol == “10GE” 8-bit control indication. bit[0] is the control signal for rx_data_64b[7:0]; bit[1] is the control signal for rx_data_64b[15:8]; …...

  • Page 43: Control And Status Signals

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Control and Status Signals Table 5.13 describes the control and status signals for 8B/10B PCS. Table 5.14 describes the control and status signals for 64B/66B PCS. Table 5.13. Control and Status Signals Functions (8B/10B PCS)

  • Page 44: Detailed Channel Block Diagram

    Detailed block diagrams in this section are intended to show you the major functionality in a single channel of the CertusPro-NX SerDes/PCS. You can find all the major blocks, clock, and data flow in these diagrams. PCI Express PCS channel is hidden in all the three modes, considering that this channel can only be used by PCI Express protocol.

  • Page 45: Figure 5.12. Detailed Channel Block Diagram Of Mpcs-8B/10B Mode

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note PCI Express PCS Channel PMA Control PRBS Ge n & Chk Cal ibration FS M E qua liza tion FS M 64B/66B PCS Channel, PMA Only Channel Quad Common, Clock Res et Generation, and BIST Gen/Chk Figure 5.12.

  • Page 46: Figure 5.14. Detailed Channel Block Diagram Of Mpcs-Pma Only Mode

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note PCI Express PCS Channel PMA Control PRBS Ge n & Chk Cal ibration FS M E qua liza tion FS M 64B/66B PCS Channel, 8B/10B PCS Channel Quad Common, Clock Res et Generation, and BIST Gen/Chk Figure 5.14.

  • Page 47: Serdes/Pcs Function Description

    SerDes/PCS Function Description CertusPro-NX devices have one to three Quads of embedded SerDes/PCS logic. Each Quad, in turn, supports four independent full-duplex data channels. A single channel can support a data link, and each Quad can support up to four such channels.

  • Page 48: Figure 6.2. Pci Express Ac Coupling Capacitors Location

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note The SerDes includes an eye monitor to map the post-equalized eye density. Eye X and Y coordinates can be controlled, and the error density can be calculated at each coordinate. The X coordinate can be set by a 6-bit bus in 1.5mVdiff (minimum) increments with a separate sign bit, and the Y coordinate by a 6-bit bus in UI/64 increments.

  • Page 49: Pma Controller

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note PMA Controller PMA Controller block is shared by all modes, as shown in Figure 6.3. PCI Express PCS is connected to PMA Controller directly, while MPCS is connected to PMA Controller via External PCS (EPCS) interface. The Tx Gear Box and Rx Gear Box can be used as 2:1 gearing buffer, when the PMA data width is set to no more than 10 bits.

  • Page 50: Mpcs

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note PCI Express PCS Gen3 8B/10B Encoder/ PIPE Tx Tx Gear 128B/130B with Scrambler PIPE FSM & LMMI I/F PCIe Power & Registers Space Controller Gen3 Word/ Elastic 8B/10B Decoder/ PIPE Rx Rx Gear...

  • Page 51: Table 6.2. Bit Mapping Of Tx Data Bus

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note 6.4.1.1. Data Bus Description The bit mapping and transfer order of 40-bit Transmitter/Receiver data bus is described as follows. The data flowing over the data bus can be either 8b data or 10b data.

  • Page 52: Table 6.3. Bit Mapping Of Rx Data Bus

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note 8b Data 10b Data Byte 1-byte Mode 2-byte Mode 4-byte Mode Transfer Ordering tx_data[10] data_1[0] data_1[0] tx_data[9] cordisp_0 data_0[9] tx_data[8] ctrl_0 data_0[8] tx_data[7] data_0[7] data_0[7] tx_data[6] data_0[6] data_0[6] tx_data[5] data_0[5] data_0[5] byte_0 used...

  • Page 53: Figure 6.6. Tx Gearing Case I

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note 8b Data 10b Data Byte 1-byte Mode 2-byte Mode 4-byte Mode Transfer Ordering rx_data[6] data_0[6] data_0[6] rx_data[5] data_0[5] data_0[5] rx_data[4] data_0[4] data_0[4] rx_data[3] data_0[3] data_0[3] rx_data[2] data_0[2] data_0[2] rx_data[1] data_0[1] data_0[1] first rx_data[0]...

  • Page 54: Figure 6.7. Tx Gearing Case Ii

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Wr Clock Wr Data D1D0 D3D2 Rd Clock Rd Data Figure 6.7. Tx Gearing Case II The phase compensation FIFO resolves clock phase difference between its read side and write side. The FIFO can signal its overflow and underflow status once they happen.

  • Page 55: Figure 6.9. Rx Gearing Case Ii

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Wr Clock Wr Data Rd Clock Rd Data D1D0 D3D2 Figure 6.9. Rx Gearing Case II This module can put the word alignment pattern (usually the control symbol) to the byte_0 (LSByte) of the 2-byte or 4-byte data bus.
  • Page 56 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note mode) directly. This forcing data mode is implemented for protocol like SLVS-EC that needs 8B/10B encoding/decoding, but needs to send some invalid 10b code sometimes. Note: The “force data” function takes precedence over “force disparity” and “invert disparity” if they are enabled simultaneously.

  • Page 57: Figure 6.11. Word Aligner Block Diagram

    To support applications which need deterministic and lower latency, CertusPro-NX SerDes/PCS also supports manual alignment mode (or bit slip mode in some documents). In manual mode, fabric can drive the skipbit signal high to control the input parallel data shifting inside PMA.

  • Page 58: Figure 6.12. Link Synchronization Fsm

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note !rst_n NO_SYNC syn_code detected bad code recieved good_code received NO_SYNC_1 bad_counter == B sync_counter == S good_code received SYNC bad_counter == 0 bad_code recieved any code received SYNC_1 Figure 6.12. Link Synchronization FSM After reset, Link Synchronization FSM enters the default state: NO_SYNC.

  • Page 59: Figure 6.13. Before 2-Byte Boundary Alignment

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note This Link Synchronization FSM can optionally be enabled or disabled. If disabled, user logic should implement the state machine to meet some criteria of synchronization or loss of synchronization and drive walign_en to request the re-alignment operation once loss of synchronization is detected.

  • Page 60: Figure 6.15. Data Stream Before Word Alignment

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Figure 6.15. Data Stream before Word Alignment After locking the data boundary, this module starts outputting aligned data: K28.5 followed by D16.2 (1010001001). Seven bits are slipped in this example. Figure 6.16. Data Stream after Word Alignment However, the number of bit slipped is always zero in manual alignment mode considering that the bit shifting is operated by PMA and controlled by fabric.

  • Page 61: Figure 6.18. The Expected Location Of Synchronization Code

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Figure 6.18. The Expected Location of Synchronization Code Tx Lane-to-lane Deskew One clock cycle lane-to-lane skew may be introduced by the uncertain latency of Tx FIFO (works as phase compensation FIFO). The Tx Lane-to-lane Deskew FIFO is implemented to eliminate this skew between two different Tx channels by using the common clock from Quad Common module.

  • Page 62: Figure 6.20. Skip Pattern Mask Code

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Figure 6.20. SKIP Pattern Mask Code This Elastic Buffer supports both 10-bit data mode (bypassing 8B/10B Decoder) and 8-bit data mode (after 8B/10B decoding). The bit mapping of 8-bit mode and 10-bit mode is shown in Figure 6.17.

  • Page 63: Figure 6.22. Lane Alignment Pattern Mask Code

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Usually the write clock is from Rx PMA of each channel, while the read clock is from the Quad Common module. Check MPCS Quad Clock Detail section for more details about the common clock.

  • Page 64: Figure 6.24. 64B/66B Pcs Channel Block Diagram

    The 10 Gigabit Media Independent Interface (XGMII) is a Double Data Rate (DDR) interface between MAC and PCS, defined by IEEE802.3 specification. CertusPro-NX device implements a Single Data Rate (SDR) MPCS-Fabric interface to replace the standard XGMII, considering that it is difficult to implement the DDR interface with FPGA fabric.

  • Page 65: Figure 6.25. Xgmii Vs. Mpcs-Fabric Interface

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note XGMII Clock TXD/RXD[31:0] TxC/RXC[3:0] MPCS-Fabric Clock Tx/Rx Data[63:0] {D1,D0} {D3,D2} {D5,D4} {D7,D6} {D9,D8} Tx/Rx Control[7:0] {C1,C0} {C3,C2} {C5,C4} {C7,C6} {C9,C8} Figure 6.25. XGMII vs. MPCS-Fabric Interface 6.4.2.2. Function Block Description Tx/Rx Gear Box The Tx/Rx Gear Box module implements 4:1 gearing functionality in order to adapt the data path between the 66-bit width of 64B/66B block and the 16-bit width of PMA data bus.

  • Page 66: Figure 6.26. 64B/66B Pcs Tx Fifo Write Operation Case I

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note The PRD Generator is loaded with a seed or its inverse at the start of a block every 128 blocks. Either 64-bit zeros or the 64-bit encoding for two Local Fault ordered sets can be selected as the data pattern, depending on seed settings. The sync header is fixed to the control sync header, 2’b10.

  • Page 67: Figure 6.27. 64B/66B Pcs Tx Fifo Write Operation Case Ii

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note tx_usr_clk almost full almost empty tx_fifo_wr tx_data/tx_control Figure 6.27. 64B/66B PCS Tx FIFO Write Operation Case II Rx FIFO The Rx FIFO module is implemented to adapt Rx path clock frequency and phase difference between 64B/66B PCS and fabric.
  • Page 68 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Character deleting occurs, if the number of data residing in Rx FIFO exceeds high water line. Character inserting occurs, if the number of data residing in Rx FIFO is lower than low water line.

  • Page 69: Figure 6.30. Pma Only Mode Block Diagram

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Tx Path Tx Lane-to-lane TX FIFO Deskew tx_usr_clk tx_pcs_clk tx_out_clk tx_pcs_clka tx_pcs_clkb tx_lalign_clk Fabric Rx Path RX FIFO rx_usr_clk rx_out_clk rx_pcs_clk Figure 6.30. PMA Only Mode Block Diagram 6.4.3.1. Data Bus Description The bit mapping of user logic data bus to PMA data bus is shown in Table 6.7.

  • Page 70: Quad Common

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note The “usr_dbus” is named as epcs_txdata_i in Tx path, or epcs_rxdata_o in Rx path. The bit[0] is transmitted/received first. Transfer ordering description:  T0: the first PMA clock cycle to capture/launch data in a data block transfer.

  • Page 71: Figure 6.31. Quad Reference Clock Source

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Figure 6.31. Quad Reference Clock Source Both SDQx_REFCLKP/N receive buffer and SD_EXTx_REFCLKP/N receive buffer can convert differential input to single-ended output to drive the clock tree. However, the detailed implementation of these two receive buffer are different.

  • Page 72: Clocks And Reset

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Clocks and Reset MPCS Channel Clock Detail This section describes the detailed implementation about the clock distribution inside MPCS channel. 8B/10B PCS channel, 64B/66B PCS channel and PMA Only channel are discussed separately.

  • Page 73: Figure 7.2. 64B/66B Pcs Channel Clock Diagram

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Clock Direction Description synchronous to this clock. rx_usr_clk Input This clock is a node of fabric clock tree. The data received by user logic from MPCS is synchronous to this clock. Channel Internal Clock tx_pcs_clka This clock drives most part of Tx path logics.

  • Page 74: Table 7.2. 64B/66B Pcs Channel Clock

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table 7.2. 64B/66B PCS Channel Clock Clock Direction Description PMA Interface (Hardened Connection) tx_pcs_clk This parallel data clock is generated by PMA Tx macro and used by MPCS to drive Tx data bus. The source of this clock is Tx PLL.

  • Page 75: Figure 7.3. Pma Only Mode Clock Diagram

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note PMA Only Mode Clock Figure 7.3 shows the PMA Only mode clock diagram. Table 7.3 shows the PMA Only mode channel clock detailed descriptions. Tx Lan e-to-lane Tx FIFO Deskew Tx User Logic...

  • Page 76: Mpcs Quad Clock Detail

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Clock Direction Description Clocks within a Quad tx_lalign_clk This is a common clock shared by channels within Quad. It is used in multiple-channel application cases. In Tx path, a common clock is used to align all channels in order to minimize the lane-to-lane skew.

  • Page 77: Mpcs Quad-To-Quad Clock Connection

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table 7.4. Quad Clock Clock Direction Description Input and Output tx_lalign_clk_out This clock is used for lane alignment across Quad boundary. It can drive multiple Quads tx_lalign_clk tree in the application case where more than four lanes (and up to twelve lanes) are combined to form a single link.

  • Page 78: Clock Frequency

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Figure 7.6. Single Quad Clock Connection Clock Frequency This section lists the recommended reference clock frequency, the PLL settings, PMA/PCS internal clock frequency, interface data bus width and clock frequency for Ethernet, SLVS-EC, CoaXPress, DP/eDP and PCIe protocols. Refer to Table 7.5...

  • Page 79: Application Case

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Application Case 8B/10B PCS Single Lane Tx Path Case I-a: Use Tx FIFO As shown in Figure 7.7, the Tx Lane-to-lane Deskew module is bypassed, considering this a single lane application. The tx_out_clk is used to drive FPGA global clock tree, and a leaf node of this clock tree returning to MPCS is used as the read clock of Tx FIFO.

  • Page 80: Figure 7.9. Case Ii-A Clock Structure

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note RX Path Fabric Word Elastic Lane 8B/10B Rx FIFO Buffer Aligner Aligner Decoder rx_pcs_clk rx_pcs_clka rx_usr_clk Clock rx_lalign_clk Tree tx_lalign_clk rx_pcs_clkb rx_out_clk tx_pcs_clk Figure 7.9. Case II-a Clock Structure Case II-b: Bypass Rx FIFO...

  • Page 81: Figure 7.12. Case Iii-A Clock Structure

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note 8B/10B PCS Multiple Lane Tx Path Case III-a: Use Tx FIFO As shown in Figure 7.12, the tx_pcs_clk0 and tx_pcs_clk1 are the generated clock from the corresponding channel PMA Tx PLL. Tx FIFO modules are enabled to eliminate the clock phase difference between tx_usr_clk and each channel internal clock (tx_out_clk0 and tx_out_clk1).

  • Page 82: Figure 7.13. Case Iv-A Clock Structure

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Channel 0 RX Path Fabric Elastic Word Lane 8B/10B Rx FIFO Aligner Buffer Aligner Decoder rx_pcs_clk0 rx_usr_clk rx_pcs_clka0 Clock rx_lalign_clk Tree tx_lalign_clk rx_pcs_clkb0 rx_out_clk0 tx_pcs_clk0 Quad Common Channel 1 RX Path Fabric Word...

  • Page 83: Figure 7.14. Case Iv-B Clock Structure

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Channel 0 RX Path Fabric Word Lane 8B/10B Elastic Buffer Rx FIFO Aligner Aligner Decoder rx_pcs_clk0 rx_pcs_clka0 Clock rx_lalign_clk Tree tx_lalign_clk rx_pcs_clkb0 rx_out_clk0 tx_pcs_clk0 Quad Common Channel 1 RX Path Fabric Word Lane...

  • Page 84: Figure 7.15. 64B/66B Pcs With Using Gpll

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note TX Path 2b sync 8b TXC 8b TXC 16b data 66b block 64B/66B + 64b data + 64b TXD + 64b TXD FIFO Scrambler Fabric Encoder Gear Box tx_usr_clk (156.25MHz) tx_pcs_clk (644.5MHz, from Tx PLL) tx_pcs_divclk (161.1328MHz)

  • Page 85: Pma Clock Divider

    These PMA clock dividers can be configured via IP GUI, primitive parameter or register accessing. SerDes/PCS Reset Reset and Power Control Signals Table 7.6 shows the reset and power control signals for CertusPro-NX SerDes/PCS. NL represents the number of lanes. Table 7.6. Reset and Power Control Signals Port Name Width...
  • Page 86 Reset Sequence This section covers the recommended reset sequence for MPCS mode and PMA Only mode. For reset sequence required by PIPE mode and PCI Express Hard IP mode, refer to CertusPro-NX PCI Express Hardened IP Core User Guide (FPGA-IPUG-XXXXX).

  • Page 87: Figure 7.18. Mpcs Mode Reset Sequence (Tx Path)

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Power Up lmmi_clk_i Valid Clock mpcs_clkin_i Valid Clock lmmi_resetn_i mpcs_perstn_i mpcs_tx_out_clk Valid Clock mpcs_ready_o mpcs_txval_i mpcs_tx_pcs_rstn_i Valid Data mpcs_tx_ch_din_i Stage Figure 7.18. MPCS Mode Reset Sequence (Tx Path) Power Up lmmi_clk_i Valid Clock...

  • Page 88: Figure 7.20. Epcs Mode Reset Sequence (Tx Path)

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Power Up lmmi_clk_i Valid Clock epcs_clkin_i Valid Clock lmmi_resetn_i epcs_rstn_i epcs_txclk_o Valid Clock epcs_ready_o epcs_txval_i epcs_tx_pcs_rstn_i Valid Data epcs_txdata_i Stage Figure 7.20. EPCS Mode Reset Sequence (Tx Path) Power Up lmmi_clk_i Valid Clock...

  • Page 89: Serdes Equalization

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note SerDes Equalization The interconnection between the transmitter and receiver device acts as a filter at typical baud rates, and distorts the serial data signal to varying extents. Figure 8.1 shows the signal distortion for the typical backplane applications. The signal out from the transmitter side is a clean digital signal, but the signal waveform is significantly distorted at the receiver side.

  • Page 90: Tx Equalization

    Figure 8.3. Typical Backplane Application with Rx Equalizer CertusPro-NX device implements both Tx equalizer and Rx equalizer for multiple protocols supporting. Tx equalizer is based on 3-tap FIR, while the Rx equalizer is based on CTLE and 1-tap DFE. Below sections descript the detailed usage of CertusPro-NX Tx equalizer and Rx equalizer.

  • Page 91: Figure 8.5. Definition Of Tx Voltage Levels

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Given a differential signal with symmetric swings above and below 0, it can be seen from Figure 8.5 that there are four possible output values in each positive or negative directions. Table 8.1 shows the positive normalized voltage levels.

  • Page 92: Rx Equalization

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Rx Equalization CertusPro-NX device implements programmable single pole-zero Continuous Timer Linear Equalizer (CTLE) at the receiver side, followed by Decision Feedback Equalization (DFE) and circuitry to support adaptation of the CTLE and DFE. Figure 8.6 shows the block diagram of receive equalizer.

  • Page 93: Serdes/Pcs Debug Capabilities

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note SerDes/PCS Debug Capabilities Loopback Mode CertusPro-NX SerDes/PCS supports up to seven loopback modes for different test purposes:  PMA Near-End Serial Loopback Mode  PMA Far-End Parallel Loopback Mode  8B/10B PCS Near-End Parallel Loopback Mode ...

  • Page 94: Figure 9.2. 8B/10B Pcs Near-End Parallel Loopback Mode

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note 8B/10B PCS Loopback The 8B/10B PCS implements two loopback modes, 8B/10B PCS Near-End Parallel Loopback Mode and 8B/10B PCS Far-End Parallel Loopback Mode. Figure 9.2 shows the block diagram of 8B/10B PCS Near-End Parallel Loopback Mode. In this mode, the 8B/10B PCS output data passes through a phase compensation FIFO (Loopback FIFO) to Rx path.

  • Page 95: Signal Detector

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note 64B/66B PCS Loopback Figure 9.4 shows three loopback modes implemented by 64B/66B PCS: Loopback Path A, Loopback Path B and Loopback Path C. In loopback path A mode, the 16-bit input data of Rx path comes from Tx path. In addition, the tx_pcs_clk is used to drive both Tx path and Rx path.

  • Page 96: Loss Of Lock

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note The threshold voltage can be configured as 125 mV or 180 mV, by accessing the bit[1] of PMA Control Register 0 [PMA reg00]. The loss of signal condition is defined in Table 9.1. After reset, if TranDet is not asserted, it means no transition exceeding the threshold voltage is detected at RxDP/RxDN.

  • Page 97: Eco Editor

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note ECO Editor The Lattice Radiant ECO Editor supports all the attributes of the primitives. The ECO Editor includes all settings that you can see in the GUI tab, including the pre-defined setting based on protocols.

  • Page 98: Serdes/Pcs Register Access

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note SerDes/PCS Register Access Register Access Bus Each SerDes/PCS channel has independent register access bus: Lattice Memory Mapped Interface (LMMI). It has the following features:  8-bit width of write and read data. ...

  • Page 99: Register Space

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Figure 10.3. Back-to-Back Write and Read Transaction Register Space Each SerDes/PCS channel has independent register space which includes following category of registers:  Configuration registers  Control registers  Status registers  Status registers with clear-on-read All register bits in Appendix A.

  • Page 100: Protocol Mode

    All CertusPro-NX SerDes/PCS quads can be configured as PCI Express PIPE mode to work with PCIe Link Layer soft IP. But only Quad0 integrates PCIe Link Layer hard IP, which can be configured as PCI Express Hard IP mode. Both PIPE mode and Hard IP mode work with PCI Express PCS, PMA Controller and PMA.

  • Page 101: Pma Only Mode

    Ethernet Mode 1000BASE-X (GigE) Mode The 1000BASE-X (or Gigabit Ethernet, GigE) mode of CertusPro-NX SerDes/PCS fully supports from the serial I/O to the GMII/SGMII interface of the IEEE 802.3 1000BASE-X Gigabit Ethernet standard. In 1000BASE-X mode, CertusPro-NX SerDes/PCS supports the clock compensation and auto-negotiation features. The auto-negotiation control logic should be implemented in FPGA fabric to work with CertusPro-NX SerDes/PCS.

  • Page 102: Table 11.2. Gige Configuration And Idle Ordered Sets Definition

    The XAUI mode of CertusPro-NX SerDes/PCS is intended for the optional interface specified by IEEE802.3 between 10G Ethernet MAC and PHY. In XAUI mode, CertusPro-NX SerDes/PCS is configured as four 2.5Gbps lanes based on 8B/10B PCS. With Lattice XAUI IP core, the XAUI mode of CertusPro-NX SerDes/PCS fully supports from serial I/O to the XGMII interface.

  • Page 103: Slvs-Ec Mode

    Sony for the next generation high resolution CMOS Image Sensor (CIS). The SLVS-EC interface provides a unidirectional wide band pixel data transfer from CIS to a Digital Signal Processor (DSP) or other digital devices. CertusPro-NX SerDes/PCS supports up to eight lanes and up to 5Gbps baud rate SLVS-EC receiver applications. Table 11.5 shows the baud grades supported by CertusPro-NX SerDes/PCS.

  • Page 104: Displayport Mode

    The DisplayPort mode of CertusPro-NX SerDes/PCS supports up to four different DisplayPort link rate: RBR, HBR, HBR2, and HBR3. In DisplayPort mode, SerDes/PCS block is configured as specific link rate, based on 8B/10B PCS.

  • Page 105: Serdes/Pcs Block Latency

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note SerDes/PCS Block Latency Table 12.1 provides transmit and receive latencies respectively in the SerDes, as well as different stages inside the PCS. The latency is in number of parallel word clocks. Table 12.1. Transmit/Receive SerDes/PCS Latency...

  • Page 106: Other Design Considerations

    To achieve a reasonable level of long-term jitter, it is vital to deliver an analog-grade power supply to the PLL. Typically, an R-C or R-L-C filter is usually used, with the “C” being composed of multiple devices to achieve a wide spectrum of noise absorption. Although the circuit is simple, there are specific board layout requirements for CertusPro-NX SerDes/PCS.

  • Page 107: Reference Clock Source Selection

    When clock from GPLL output is used as the reference clock for CertusPro-NX SerDes/PCS, the reference clock to the GPLL should be assigned to the dedicated GPLL input pad. However, the GPLL output jitter may not meet system specifications at higher data rates.

  • Page 108: Spread Spectrum Clocking Support

    Transmitter. What should be noted is that the reference clock from RC needs to be used in PCI Express Endpoint applications based on CertusPro-NX SerDes/PCS, when the SSC feature has been enabled. Otherwise, reference clock source from local OSC can be used for CertusPro-NX SerDes/PCS.

  • Page 109: Electrical Idle

    Electrical Idle is a steady state condition where the transmitter TxDP and TxDN voltages are held constant with the same value. Electrical Idle is primarily used in power savings and inactive states. CertusPro-NX SerDes/PCS supports three types of Electrical Idle: EI1, EI2, and EI4.

  • Page 110: Serdes/Pcs Generation In Radiant Software

    SerDes/PCS Generation in Radiant Software CertusPro-NX SerDes/PCS can be configured and implemented by MPCS foundational IP that is provided by IP Catalog tool in Lattice Radiant software. There are three types of primitives named, PCSX1, PCSX2, and PCSX4. PCSX1 is for single channel applications based on CertusPro-NX SerDes/PCS block.

  • Page 111: Attribute Summary

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Protocol Name Descriptions QSGMII QSGMII PCIE PCI Express Hard IP mode (not for user implementation) PCIE-PCS PCI Express PIPE mode SGMII SGMII SLVS_EC SLVS-EC XAUI XAUI G8B10B Generic 8B/10B PMA_ONLY PMA Only Attribute Summary The configurable attributes of the MPCS foundational IP are listed in Table 14.2...
  • Page 112 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Attribute Selectable Values Default Dependency on Other Attributes name followed by suffix “_PCSGRP”. Always uneditable. Mode “Rx_only”, “Tx_only”, “Rx_and_Tx” If Protocol == “PCIE”, value is “Rx and “Rx_and_Tx” Tx”; If Protocol == “RXAUI”, value is “Rx and Tx”;...
  • Page 113 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Attribute Selectable Values Default Dependency on Other Attributes External IO Pad Ref Clk for “IO Pad0”, “IO Pad0” Active if RefClk Selection for Quad0 Quad0 == “External IO Pad” “IO Pad1” “X4 mode”, “X2 mode”, “X1 “X4 mode”...
  • Page 114 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Attribute Selectable Values Default Dependency on Other Attributes Number of Valid Sync Code (0 – 255) Active if (Word Alignment == Groups “ENABLED”) and (Use ‘sync_det’ FSM == “ENABLED”) Number of Bad Code (0 –...

  • Page 115: Table 14.3. Attributes Descriptions

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Attribute Selectable Values Default Dependency on Other Attributes “6_SKEW”, “7_SKEW”, “8_SKEW”, “9_SKEW”, “10_SKEW”, Primary Lane Alignment Active if Lane Alignment == Pattern Byte 0 (HEX) “ENABLED” Primary Lane Alignment Active if Lane Alignment == Pattern Byte 1 (HEX) “ENABLED”...
  • Page 116 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Attribute Description TX MPCS Reset When enabled, MPCS module soft resets the TX path (not including the register space). For more details, refer to register field tx_mpcs_rst in Table A. TX Phase Compensation FIFO Specifies whether the TX phase compensation FIFO is enabled or disabled.

  • Page 117: Primitive

    Near End Parallel Loopback — Far End Parallel Loopback — Primitive Table 14.4 shows the pin-to-pin connection between CertusPro-NX SerDes/PCS primitive and MPCS foundational IP. Table 14.4. Pin-to-Pin Connection MPCS Foundational IP Port – Primitive Ports MPCS Foundational IP Port – PIPE MPCS/EPCS...
  • Page 118 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note MPCS Foundational IP Port – Primitive Ports MPCS Foundational IP Port – PIPE MPCS/EPCS CH[3:0]_LMMIREADY lmmi_ready_o lmmi_ready_o CH[3:0]_LMMIRDATA lmmi_rdata_o lmmi_rdata_o CH[3:0]_SDRXP sd[n]_rxp_i sd[n]_rxp_i CH[3:0]_SDRXN sd[n]_rxn_i sd[n]_rxn_i CH[3:0]_SDTXP sd[n]_txp_o sd[n]_txp_o CH[3:0]_SDTXN sd[n]_txn_o sd[n]_txn_o CH[3:0]_SDREXT...
  • Page 119 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note MPCS Foundational IP Port – Primitive Ports MPCS Foundational IP Port – PIPE MPCS/EPCS CH[3:0]_PIPE_TX_DATA_VLD mpcs_tx_ch_din_i [73:56]/ pipe_tx_data_vld_i epcs_txdata_i [73:56] CH[3:0]_ PIPE_REMOTE_FS_PCS_TX_DATA mpcs_tx_ch_din_i [53:48]/ pipe_remote_fs_pcs_tx_data_i epcs_txdata_i [53:48] CH[3:0]_ PIPE_REMOTE_LF_PCS_TX_DATA {mpcs_tx_ch_din_i [55:54], pipe_remote_lf_pcs_tx_data_i mpcs_tx_ch_din_i [74:44]}/...
  • Page 120 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note MPCS Foundational IP Port – Primitive Ports MPCS Foundational IP Port – PIPE MPCS/EPCS CH[3:0]_PIPE_RXEQ_DIR_PCS_RX_FIFO_ST mpcs_rx_fifo_st_o[3:2] pipe_rxeq_dir_pcs_rx_fifo_st_o CH[3:0]_PCS_RX_HI_BER mpcs_rx_hi_ber_o — CH[3:0]_PCS_RX_BLK_LOCK mpcs_rx_blk_lock_o — CH[3:0]_PCS_TX_FIFO_ST mpcs_tx_fifo_st_o[3:2] — CH[3:0]_ PIPE_TX_DATA_EN mpcs_tx_fifo_st_o[1] pipe_tx_data_en_o CH[3:0]_ PIPE_LOCAL_GET_TX_COEF_VLD mpcs_tx_fifo_st_o[0]...
  • Page 121 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note MPCS Foundational IP Port – Primitive Ports MPCS Foundational IP Port – PIPE MPCS/EPCS CH[3:0]_PIPE_TX_ELEC_IDLE_LL — pipe_tx_elec_idle_LL_i CH[3:0]_PIPE_RX_DATAEN_LL — pipe_rx_data_enable_LL_o CH[3:0]_PIPE_RX_DATA_VALID_LL — pipe_rx_data_valid_LL_o CH[3:0]_PIPE_RX_START_BLOCK_LL — pipe_rx_start_block_LL_o CH[3:0]_PIPE_RX_SYNC_HEADER_LL — pipe_rx_sync_header_LL_o CH[3:0]_PIPE_BLOCK_ALIGN_CONTROL_LL — pipe_block_align_control_LL_i CH[3:0]_PIPE_RX_DATA_LL —...

  • Page 122: Appendix A. Configuration Registers

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Appendix A. Configuration Registers A.1. PMA Registers A.1.1. Register Address Table A. 1. Register Address Offset Access Register Name Description LMMI Type 8’d0 reg00 Control register 0. 8’d1 reg01 Clock count for error counter decrement.

  • Page 123: Table A. 3. Clock Count For Error Counter Decrement [Reg01]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description always detected. 1’b1 – the result is always detected. 1’b0 – normal operation (this bit should be set to 1’b0 for other protocols). [5:4] CDR reference 2’b00 Defines the CDR PLL reference clock mode.

  • Page 124: Table A. 7. Tx Pll M & N Settings [Reg05]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description Divider). PCLK is used by the PCIe PCS logic as well as by the majority of the PMA control logic, and thus is also useful for other protocol in order to reduce the amount of logic requiring high TxClk frequency.

  • Page 125: Table A. 9. Rx Pll M & N Settings [Reg07]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 9. Rx PLL M & N Settings [reg07] Field Name Access Width Reset Description reserved RSVD 1’b0 — [6:5] 2’b10 Defines the CDRPLL M setting. 2’b11 – 8 2’b10 – 4 2’b01 –...

  • Page 126: Table A. 13. Tx Pre-Cursor Ratio [Reg0B]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 13. Tx Pre-Cursor Ratio [reg0b] Field Name Access Width Reset Description [7:0] tx_pre_ratio 8’h00 This register defines the Tx pre-cursor ratio for PCI Gen1 speed or non-PCIe protocols. A value of 8’d128 corresponds to 100% (full voltage) whereas a value of 8’d0...

  • Page 127: Table A. 15. Tx Amplitude Ratio [Reg18]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 15. Tx Amplitude Ratio [reg18] Field Name Access Width Reset Description [7:0] tx_amp_ratio 8’h80 This register implements the Tx amplitude ratio used by the Tx driver. A value of 128 corresponds to 100% (full voltage) whereas a value of 0 corresponds to 0%.

  • Page 128: Table A. 20. Prbs Control Register [Reg64]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description calibration sequence after power-up and PHY reset de-assertion. 1’b1 – completed. 1’b0 – not yet. reserved RSVD 1’b0 — arxctle_err Defines Rx CTLE calibration has reached a minimum or maximum value.

  • Page 129: Table A. 21. Prbs Error Counter Register [Reg65]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 21. PRBS Error Counter Register [reg65] Field Name Access Width Reset Description [7:0] prbs_errcnt 8’h00 Reports the number of PRBS error detected when the PRBS test is applied. This register is automatically cleared when the prbs_chk bit gets cleared.

  • Page 130: Table A. 25. Receive Pll Current Charge Pump [Reg6A]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description non-PCIe protocols. Note: This register can be reprogrammed when the PHY is under reset. Table A. 25. Receive PLL Current Charge Pump [reg6a] Field Name Access Width...

  • Page 131: Table A. 27. Cdr Pll Manual Control [Reg79]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description 1’b0 – normal operation. plesio_lpbk 1’b0 Enables the plesiochronous loopback mode which forces the PCS to loopback data from Rx back to Tx after the PCIe elastic buffer function. It is equivalent to PCIe slave loopback except that it is forced by a register instead of controlled by the PCIe MAC layer.

  • Page 132: A.2. Mpcs Registers

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 29. Update Settings Command Register [reg80] Field Name Access Width Reset Description [7:1] reserved RSVD 7’h0 — reg_apply 1’b0 This bit is transient (read always report 0) where writing 1’b1 to this bit will trigger a new computation of PMA settings based on values written into related PMA registers.
  • Page 133 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Offset LMMI Register Name Access Type Description 8’h4d reg4d Sync_Det Pattern Mask Code MSB. 8’h50 reg50 Lane Alignment Control. 8’h51 reg51 Maximum Lane-to-lane Skew. 8’h52 reg52 Primary Lane Alignment Pattern Byte 0. 8’h53 reg53 Primary Lane Alignment Pattern Byte 1.

  • Page 134: A.2.2. Register Description

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Offset LMMI Register Name Access Type Description 8'h9c reg9c 10GBASE-R Test Pattern Seed B Byte2. 8'h9d reg9d 10GBASE-R Test Pattern Seed B Byte3. 8'h9e reg9e 10GBASE-R Test Pattern Seed B Byte4. 8'h9f reg9f 10GBASE-R Test Pattern Seed B Byte5.

  • Page 135: Table A. 32. Tx Path Control [Reg10]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description selected source/interface for the Tx Path. 1’b1 – use rx_pcsmode_sel to override the MODESEL to set the MPCS mode for the Tx path. 1’b0 – use the MODESEL to set the MPCS mode for the Tx path.

  • Page 136: Table A. 34. Rx Path Control [Reg20]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description enc_8b10b_interleave 1’b0 8B/10B Encoder Interleave. Specifies whether the 8B/10B Encoder Interleave is enabled or disabled. 1’b1 – enabled. 1’b0 – disabled. Table A. 34. Rx Path Control [reg20]...

  • Page 137: Table A. 36. 8B/10B Decoder Control [Reg22]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description rfifo_byte_shift 1’b0 Byte shift. Specifies the data shift caused by COMMA byte alignment operation. 1’b1 – there is one byte data shift. 1’b0 – there is no byte shift.

  • Page 138: Table A. 39. Primary Word Alignment Pattern Byte 1 [Reg32]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 39. Primary Word Alignment Pattern Byte 1 [reg32] Field Name Access Width Reset Description [7:0] pri_wa_ptn [17:10] 8’h0 Specifies the 20-bit primary word alignment pattern. In 10-bit width mode, only bits 9 to 0 are applied.

  • Page 139: Table A. 46. Word Alignment Pattern Mask Code Msb [Reg39]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description is not ignored during alignment pattern matching. Table A. 46. Word Alignment Pattern Mask Code MSB [reg39] Field Name Access Width Reset Description [7:4] reserved RSVD —...

  • Page 140: Table A. 51. Number Of Bit Slipped During Word Alignment [Reg3E]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description check is enabled or disabled. 1’b1 – the first byte of sync_det pattern must appear on N-byte boundary, where N is the sync_det pattern length defined by sync_ptn_len register. Once a...

  • Page 141: Table A. 57. Secondary Sync_Det Pattern Byte 0 [Reg44]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 57. Secondary Sync_Det Pattern Byte 0 [reg44] Field Name Access Width Reset Description [7:0] sec_sdptn_byte0 8’h7c Secondary Sync_Det Pattern Byte 0. Table A. 58. Secondary Sync_Det Pattern Byte 1 [reg45] Field...

  • Page 142: Table A. 67. Lane Alignment Control [Reg50]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 67. Lane Alignment Control [reg50] Field Name Access Width Reset Description [7:5] reserved RSVD — — sec_laptn_en 1’b0 Secondary Lane Alignment. Specifies if the secondary lane alignment pattern matching is enabled or disabled.

  • Page 143: Table A. 72. Primary Lane Alignment Pattern Byte 3 [Reg55]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 72. Primary Lane Alignment Pattern Byte 3 [reg55] Field Name Access Width Reset Description [7:0] pri_laptn_byte3 8’h0 Primary Lane Alignment Pattern Byte 3. Table A. 73. Primary Lane Alignment Pattern Byte MSB [reg56]...

  • Page 144: Table A. 80. Clock Frequency Compensation Control [Reg60]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 80. Clock Frequency Compensation Control [reg60] Field Name Access Width Reset Description [7:6] reserved RSVD — — sec_skip_en 1’b0 Enable Secondary Skip. Specifies the secondary skip pattern is enabled or disabled.

  • Page 145: Table A. 83. Elastic Fifo Low Water Line [Reg63]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 83. Elastic FIFO Low Water Line [reg63] Field Name Access Width Reset Description [7:5] reserved RSVD — — Specifies the Clock Compensation FIFO low water line. [4:0] low_water_line 5’b01010 Mean is 5’b10000.

  • Page 146: Table A. 93. Secondary Skip Pattern Msb [Reg6D]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 93. Secondary SKIP Pattern MSB [reg6d] Field Name Access Width Reset Description [7:6] sec_skip_byte3[9:8] 2’h0 Secondary SKIP Pattern MSB Register reflects the bits 9 to 8 of Secondary SKIP Pattern byte 3 to 0.

  • Page 147: Table A. 99. 64B/66B Pcs Ctc High Water Line Control [Reg84]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description 1’b0 – Only delete one sequence ordered set each time when doing clock frequency compensation. pcs_64b66b_nofpll 1’b0 1’b1 – No GPLL is used to generate user clock.

  • Page 148: Table A. 103. 10Gbase-R Block Error Counter [Reg91]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 103. 10GBASE-R Block Error Counter [reg91] Field Name Access Width Reset Description [7:0] errored_block_count RO/CR 8’h0 10GBASE-R Block Error Counter register reflects the errored blocks counter is an eight-bit count defined by the errored_block_count counter specified in 49.2.14.2 for...

  • Page 149: Table A. 111. 10Gbase-R Test Pattern Seed A Byte 7 [Reg99]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 111. 10GBASE-R Test Pattern Seed A Byte 7 [reg99] Field Name Access Width Reset Description [7:0] prtp_seed_a[57:56] 8’h0 This register defines byte 7 of 10GBASE-R PCS test pattern seed A. Table A. 112. 10GBASE-R Test Pattern Seed B Byte 0 [reg9a]...

  • Page 150: Table A. 120. 10Gbase-R Test Pattern Control 0 [Rega2]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 120. 10GBASE-R Test Pattern Control 0 [rega2] Field Name Access Width Reset Description [7:5] tx_sw_pattern 3’d0 Defines the square wave repeating pattern of n ones followed by n zeros, where n is configurable between 4 and 11.

  • Page 151: Table A. 122. 10Gbase-R Test Pattern Error Counter Byte 0 [Rega4]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description 1’b1 – Zeros data pattern. 1’b0 – LF data pattern. Table A. 122. 10GBASE-R Test Pattern Error Counter Byte 0 [rega4] Field Name Access Width Reset Description...

  • Page 152: Table A. 126. Loopback Mode Control [Rege0]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Field Name Access Width Reset Description "1". 1’b0 – drive "epcs_txval" low if "txval_ovrd" is set to "1". Table A. 126. Loopback Mode Control [rege0] Field Name Access Width Reset Description [7:3] reserved RSVD —...

  • Page 153: Table A. 128. Mpcs Bist Control 1 [Rege2]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 128. MPCS BIST Control 1 [rege2] Field Name Access Width Reset Description [7:6] bist_ch_sel 2’b0 BIST Channel Selector. Specifies the selected BIST Channel. 2’b11 – MPCS channel_3. 2’b10 – MPCS channel_2.

  • Page 154: Table A. 132. User Defined Bist Constant 2 Byte_0 [Rege6]

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table A. 132. User Defined BIST Constant 2 Byte_0 [rege6] Field Name Access Width Reset Description [7:0] udbc2[17:10] 8’h0 User-defined BIST Constant 1 Byte_0 register reflects the lower 8 bits of the 10b User-defined BIST Constant value pattern 1.

  • Page 155: Appendix B. 8B/10B Symbol Coding

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Appendix B. 8B/10B Symbol Coding Table B. 1 shows the 8B/10B encoding for data characters. Table B. 2 shows the 8B/10B encoding for control characters. Table B. 1. 8B/10B Data Symbol Codes Data Byte Name...
  • Page 156 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Data Byte Name Data Byte Value (Hex) Data Byte Value (Bin) Coded Data Value (RD-) Coded Data Value (RD+) D11.1 001 01011 110100 1001 110100 1001 D12.1 001 01100 001101 1001 001101 1001 D13.1...
  • Page 157 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Data Byte Name Data Byte Value (Hex) Data Byte Value (Bin) Coded Data Value (RD-) Coded Data Value (RD+) D27.2 010 11011 110110 0101 001001 0101 D28.2 010 11100 001110 0101 001110 0101 D29.2...
  • Page 158 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Data Byte Name Data Byte Value (Hex) Data Byte Value (Bin) Coded Data Value (RD-) Coded Data Value (RD+) D11.4 100 01011 110100 1101 110100 0010 D12.4 100 01100 001101 1101 001101 0010 D13.4...
  • Page 159 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Data Byte Name Data Byte Value (Hex) Data Byte Value (Bin) Coded Data Value (RD-) Coded Data Value (RD+) D27.5 101 11011 110110 1010 001001 1010 D28.5 101 11100 001110 1010 001110 1010 D29.5...

  • Page 160: Table B. 2. 8B/10B Control Symbol Codes

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Data Byte Name Data Byte Value (Hex) Data Byte Value (Bin) Coded Data Value (RD-) Coded Data Value (RD+) D11.7 111 01011 110100 1110 110100 1000 D12.7 111 01100 001101 1110 001101 0001 D13.7...

  • Page 161: Appendix C. Calculating Parameters For Serdes Pll

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Appendix C. Calculating Parameters for SerDes PLL Table C. 1 lists the recommended parameters for SerDes PLL in specific data rate. For detailed information about PLL clock setting, refer to PLL Clock Setting section.
  • Page 162 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Bit Rate Reference Clock Note (Gbps) (MHz) (MHz) (MHz) (MHz) 6480 1620 — 6480 1620 — 8000 2000 — 83.333 8000 2000 PMA Only 8000 2000 — 8000 2000 — 8000 2000 PMA Only...
  • Page 163 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Bit Rate Reference Clock Note (Gbps) (MHz) (MHz) (MHz) (MHz) 10000 2500 — 156.25 10000 2500 156.25 PMA Only 156.25 10000 2500 312.5 PMA Only 84.375 5400 2700 168.75 PMA Only 84.375 5400 2700 337.5...
  • Page 164 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Bit Rate Reference Clock Note (Gbps) (MHz) (MHz) (MHz) (MHz) 117.1875 7500 3750 234.375 PMA Only 117.1875 7500 3750 468.75 PMA Only 7500 3750 — 156.25 7500 3750 468.75 PMA Only 8000 4000 —...
  • Page 165 CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Bit Rate Reference Clock Note (Gbps) (MHz) (MHz) (MHz) (MHz) 5.94 74.25 5940 5940 — 74.25 5940 5940 371.25 PMA Only 92.8125 5940 5940 371.25 PMA Only 5940 5940 — 123.75 5940 5940 371.25...

  • Page 166: Table C. 2. Serial Protocol Applications

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Table C. 2 shows some potential serial protocol applications based on CertusPro-NX SerDes/PCS. Table C. 2. Serial Protocol Applications Protocol Bit Rate (Gbps) Reference Clock Available Coding SerDes/PCS Mode PCIe 83.333, 100, 125...

  • Page 167: Appendix D. Using Reveal Serdes Debug Tool

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Appendix D. Using Reveal SerDes Debug Tool FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor All rights reserved. CONFIDENTIAL...

  • Page 168: References

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note References  High-Speed PCB Design Considerations (FPGA-TN-02178)  Electrical Recommendations for Lattice SERDES (FPGA-TN-02077)  ECP5 and ECP5-5G Family Data Sheet (FPGA-DS-02012)  LatticeECP3 Family Handbook (HB1009)  LatticeECP3 Family Data Sheet (FPGA-DS-02074) ...

  • Page 169: Technical Support Assistance

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport. FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor All rights reserved. CONFIDENTIAL...

  • Page 170: Revision History

    CertusPro-NX SerDes/PCS Usage Guide Preliminary Technical Note Revision History Revision 0.81, May 2021 Section Change Summary Initial preliminary release. Revision 0.70, January 2021 Section Change Summary Advance release. © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81 All rights reserved. CONFIDENTIAL...
  • Page 171 www.latticesemi.com...

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