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S
Data
t
LOW
t
f
S
CLK
t
HD;STA
S
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are
issued.
6.6. Two-Wire Serial Bus Characteristics
Table 6.5. Two-Wire Serial Bus Characteristics
Parameter
S
Clock Frequency
CLK
Hold Time (Repeated) START
Condition (after this period, the First
Clock Pulse is generated)
LOW Period of the S
Clock
CLK
HIGH Period of the S
Clock
CLK
Set-Up Time for a Repeated START
Condition
Data Hold Time
Data Set-Up Time
Rise Time of both S
and S
DATA
Fall Time of both S
and S
DATA
CLK
Set-Up Time for STOP Condition
Bus Free Time between a STOP and
START Condition
Capacitive Load for each Bus Line
Serial Interface Input Pin Capacitance
S
Max Load Capacitance
DATA
S
Pull-Up Resistor
DATA
Notes:
1.
(f
= 27 MHz; V
= 1.2 V; V
EXTCLK
DD
2
2.
This table is based on I
C standard (v2.1 January 2000) Philips Semiconductor.
2
3.
Two-wire control is I
C-compatible.
4.
All values referred to V
IHmin
5.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling
edge of SCLK. The two-wire standard specifies a minimum rise and fall time for Fast Mode operation. This specification is not a
timing requirement that is enforced on ON Semiconductor sensor's as a receiver, because our receivers are designed to work in
mixed systems with std-mode where no such minimum rise and fall times are required/specified. However, it is the host's
responsibility when using fast edge rates, especially when two-wire slew-rate driver control is not available, to manage the
generated EMI, and the potential voltage undershoot on the sensor receiver circuitry, to avoid activating sensor ESD diodes and
current-clamping circuits. This is typically not an issue in most applications., but should be checked if below minimum fall times
and rise times are required. A device must internally provide a hold time of at least 300 ns for the S
undefined region of the falling edge of S
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1
t
t
t
f
SU;DAT
r
t
t
HIGH
HD;DAT
Figure 6.1. Two-Wire Serial Bus Timing Parameters Diagram
Symbol
f
SCL
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
Signals
t
CLK
r
Signals
t
f
t
SU;STO
t
BUF
C
b
CIN_SI
CLOAD_SD
RSD
_IO = 2.8 V; V
= 2.8 V; V
DD
AA
= 0.9 V V
_IO and V
= 0.1 V
DD
ILmax
.
CLK
t
HD;STA
t
SU;STA
Sr
Standard Mode
Min
Max
0
100
4.0
—
4.7
—
4.0
—
4.7
—
5
6
0
3.45
250
—
—
1000
—
300
4.0
—
4.7
—
—
400
—
3.3
—
30
1.5
4.7
_PIX = 2.8 V; V
_PHY = 1.2 V; V
AA
DD
_IO levels. Sensor EXCLK = 27 MHz.
DD
Lattice mVision AR0234 Sensor Board
User Guide
t
BUF
t
r
t
SU;STO
P
Fast Mode
Min
Max
0
400
0.6
—
1.3
—
0.6
—
0.6
—
7
6
0
0.9
7
100
8
20 + 0.1 Cb
8
20 + 0.1 Cb
0.6
—
1.3
—
—
400
—
3.3
—
30
1.5
4.7
_PHY = 1.8 V; T
= 25 °C)
DDIO
A
signal to bridge the
DATA
S
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
pF
pF
pF
kΩ
17
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