GE Corometrics 170 Series Service Manual page 81

Processor
Address/Data
and Control
Revision C
Theory of Operation: Main Board Theory of Operation
System Flash ROM
Decoder Bank 1
System Flash ROM
Decoder Bank 2
Recorder Control
Decoder and Latch
• Head strobes
• Head supply control
• Head protection
Recorder Control
Latch Decoder
Motor phase latches
General Decoder and Latch
• SPI (serial peripheral
interface) chip selects
• Front-end/telemetry control
Battery RAM/RTC Decoder
Status Port Decoder
• Front panel buttons
• Recorder status
Display Decoder
UART Decoder
Recorder Printhead
Data Shift Register
Figure 5-12. PAL Block Diagram
170 Series Monitor
2000947-004
5-21