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DM240-DVB High-Speed Digital Modulator
<1>
Latched Major
Alarm
<1>
Latched Minor
Alarm
<1>
Latched Common
Fault
<1>
Reserved
<1>
+5 Voltage
<1>
+12 Voltage
<1>
-12 Voltage
<2>
Reserved
<2>
Reserved
<1>
Last Rate Status 0 = Symbol Rate, 1 = Data Rate
<1>
Active PIIC Slot
TM083 – Rev. 3.0
Bit 0 = Spare
Bit 1 = Transmit Oversample PLL Lock
Bit 2 = FPGA Config Error
Bit 3 = IF Synthesizer PLL Lock
Bit 4 = External Reference PLL Lock
Bit 5 = SCT PLL Lock
Bit 6 = Spare
Bit 7 = Spare
0 = Pass, 1 = Fail
Bit 0 = Spare
Bit 1 = Loss Terrestrial Clock
Bit 2 = Loss Terrestrial Data
Bit 3 = FIFO Error
Bit 4 = Spare
Bit 5 = Terrestrial Framing Error
Bit 6 = Spare
Bit 7 = Spare
0 = Pass, 1 = Fail
Bit 0 = -12 V Alarm
Bit 1 = +12 V Alarm
Bit 2 = +5 V Alarm
Bit 3 = Spare
Bit 4 = Spare
Bit 5 = Spare
Bit 6 = Spare
Bit 7 = Spare
0 = Pass, 1 = Fail
TBD
+5 V. Implied Decimal Point. Ex: 49 = +4.9 V
+12 V. Implied Decimal Point. Ex: 121 = +12.1 V
-12 V. Implied Decimal Point and Minus Sign.
Ex: 118 = -11.8 V
TBD
TBD
Without Multi-PIIC Card:
1
With Multi-PIIC Card:
1 – 3
Appendix A
A
-11
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