Table of Contents
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Appendix A
<1>
Tx Interface
Type
<1>
Input Clock
Polarity
<1>
Data Polarity
<1>
Input Clock
Source
<1>
Reserved
<11>
Reserved
<1>
Reserved
<1>
Major Alarm
Mask
<1>
Minor Alarm
Mask
A-4
0 = Serial,
1 = Parallel,
2 = ASI_Norm,
3 = ASI_Null,
4 = G.703E3,
5 = G.703T3,
6 = G.703STS-1,
7 = HSSI,
8 = Parallel DVB,
9 = Parallel M2P,
10 = None,
13 = OC3,
14 = STM-1,
15 = G.703E2,
16 = G.703T2Bal,
17 = G.703T2Unbal,
18 = G.703E1Bal,
19 = G.703E1Unbal,
20 = G.703T1AMI
21 = G.703T1B8ZS
0 = Normal, 1 = Inverted
0 = Normal, 1 = Inverted
0 = SCTE, 1 = SCT
TBD, Default = 0
TBD
TBD
Bit 0 = Spare
Bit 1 = Transmit Oversample PLL Lock
Bit 2 = FPGA Config Error
Bit 3 = IF Synthesizer PLL Lock
Bit 4 = External Reference PLL Lock
Bit 5 = SCT PLL Lock
Bit 6 = Spare
Bit 7 = Spare
0 = Mask, 1 = Allow
Bit 0 = Spare
Bit 1 = Loss Terrestrial Clock
Bit 2 = Loss Terrestrial Data
Bit 3 = FIFO Error
Bit 4 = Spare
Bit 5 = Terrestrial Framing Error
Bit 6 = Spare
Bit 7 = Spare
0 = Mask, 1 = Allow
DM240-DVB High-Speed Digital Modulator
TM083 – Rev. 3.0
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