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MOUNT
J1
3
2
4
1
MCU_PWR
OUT
USB_PWR
MOUNT
3P3V
POL_PG
IN
3P3V_PG
IN
MSTR_EN
1
P0.1
2
P0.0
3
GND
U8
R22
4
UNNAMED_3_SMRES_I230_A
UNNAMED_3_C8051F320_I232_DP
D+
R23
0
C8051F320
5
UNNAMED_3_SMRES_I231_A
UNNAMED_3_C8051F320_I232_DN
D-
0
6
VDD
7
REGIN
8
C21
VBUS
0.1UF
C22
UNNAMED_3_C8051F320_I232_RSTC2CK
UNNAMED_3_C8051F320_I232_P30
1UF
R25
1K
3P3V
1
3
UNNAMED_3_HEADERDUALROW_I252_IN1
5
7
9
FIGURE 23. ISLUSBPWRDONGLE1Z SCHEMATIC (1 OF 2)
UNNAMED_3_SMLED_I234_A
POL_SEL0
POL_SEL1
UNNAMED_3_C8051F320_I232_P06
POL_SEL[0..2]
24
P1.2
POL_SEL2
23
P1.3
EN_3P3V
22
P1.4
21
P1.5
20
P1.6
19
P1.7
18
P2.0
17
P2.1
PLACE AT RIGHT EDGE OF BOARD.
RIGHT ANGLE FEMALE CONNECTOR
2
PGR
PGR
4
PGR
PGR
UNNAMED_3_HEADERDUALROW_I250_IN1
6
PGR
PGR
8
PGR
PGR
R29
DRAWN BY:
10
PGR
PGR
10K
PROGRAM HEADER
RELEASED BY:
UPDATED BY:
OUT
OUT
OUT
SDA
2
1
SCL
2
1
4
3
4
3
OUT
6
5
6
5
3P3V
UNIVERSAL6
DATE:
Ryan Roderick
DATE:
DATE:
TESTER
MSTR_EN
ENGINEE
Rya
TITLE:
Si L
U
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