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ISL68300EVAL3Z
User's Manual: Evaluation Board
Core Power Solutions
Rev 0.00
Jul 2018

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Summary of Contents for Renesas ISL68300EVAL3Z

  • Page 1 ISL68300EVAL3Z User’s Manual: Evaluation Board Core Power Solutions Rev 0.00 Jul 2018...
  • Page 2: Specifications

    The ISL68300EVAL3Z evaluation board is a 2.7inx3.0in 6-layer FR4 board with 2oz. copper on all layers. This evaluation board comes with a placeholder for pin-strap resistors to adjust output voltage, switching frequency, and the device PMBus address.
  • Page 3: Recommended Equipment

    SYNC ISENP ISENN VSENP VSENN TEMP/ ISHARE VOUT SALRT SGND PGND ISL68300 V1P5 BOOT VSET/SA SYNC ISENP ISENN VSENP VSENN TEMP/ ISHARE PMBus SALRT SGND PGND Figure 1. ISL68300EVAL3Z Block Diagram UG173 Rev.0.00 Page 3 of 22 Jul 12, 2018...
  • Page 4: Functional Description

    2. Functional Description Functional Description The ISL68300EVAL3Z provides all circuitry required to evaluate the features of the ISL68300. A majority of the features of the ISL68300, such as compensation-free ChargeMode control, soft-start delay and ramp times, supply sequencing, and voltage margining are available on this evaluation board. For sequencing evaluation, the board can be connected to any Renesas digital module evaluation board that supports the Digital-DC™...
  • Page 5: Quick Start Guide

    PowerNavigator tutorial videos are available on the Renesas website. To sequence using the Digital-DC Bus (DDC), or to evaluate multiple Renesas digital power products using a single ZLUSBEVAL3Z dongle, the ISL68300 can be daisy chained with other digital power evaluation boards.
  • Page 6: Pcb Layout Guidelines

    Connect to ZLUSBEVAL3Z Dongle. For Multiple Board Evaluation, Connect to PMBus Dongle Out Connection of Other Board Figure 2. ISL68300EVAL3Z Evaluation Board (Top Side) Figure 3. ISL68300EVAL3Z Evaluation Board (Bottom Side) UG173 Rev.0.00 Page 6 of 22 Jul 12, 2018...
  • Page 7 ISL68300EVAL3Z Board Schematic GSW1 ISN1 ISP1 Address=0x62 Vout= 1V Fsw = 400kHz IOC = Set by Firmware ASCR = Set by Firmware GSW2 ISN2 ISP2 Address=0x63 Vout= 1V Fsw = 400kHz IOC = Set by Firmware ASCR = Set by Firmware...
  • Page 8 Monitor Vout Monitor Figure 5. Schematic - Input and Output Filters...
  • Page 9 GND3 DDC1 SDA1 SCL1 SYNC1 PREQUEL SEQUEL ZSC1 ZSC2 ZSC3 ZSC4 ZSO1 ZSO2 ZSO3 ZSO4 Figure 6. Schematic - I C, Enable, PG...
  • Page 10 Load Monitor Figure 7. Schematic - Dynamic Load...
  • Page 11: Bill Of Materials

    ISL68300EVAL3Z 3. PCB Layout Guidelines Bill of Materials Reference Designator Description Manufacturer Manufacturer Part C1, C2, C12, CAP, SMD, 0805, 10µF, 16V, 10%, X6S, ROHS C2012X6S1C106K085AC C30, C34, CAP, SMD, 1206, 150µF, 6.3V, 20%, X5R, ROHS Murata GRM31CR60J157ME11L C52, C53...
  • Page 12 ISL68300EVAL3Z 3. PCB Layout Guidelines Reference Designator Description Manufacturer Manufacturer Part R2, R7 RES, SMD, 0402, 2.2Ω, 1/16W, 1%, TF, ROHS Yageo RC0402FR-072R2L R30, R31 RES, SMD, 0402, 4.3Ω, 1/16W, 5%, TF, ROHS Vishay/Dale CRCW04024R30FKED RES, SMD, 0402, 0Ω, 1/16W, 5%, TF, ROHS...
  • Page 13 3. PCB Layout Guidelines Reference Designator Description Manufacturer Manufacturer Part C43, C45, DO NOT POPULATE C47, C59, ISL68300EVAL3Z Board Layout Figure 8. PCB - Top Silk Screen Figure 9. PCB - Top Layer UG173 Rev.0.00 Page 13 of 22 Jul 12, 2018...
  • Page 14 ISL68300EVAL3Z 3. PCB Layout Guidelines Figure 10. PCB - Inner Layer - Layer 2 (Top View) Figure 11. PCB - Inner Layer - Layer 3 (Top View) UG173 Rev.0.00 Page 14 of 22 Jul 12, 2018...
  • Page 15 ISL68300EVAL3Z 3. PCB Layout Guidelines Figure 12. PCB - Inner Layer - Layer 4 (Top View) Figure 13. PCB - Inner Layer - Layer 5 (Top View) UG173 Rev.0.00 Page 15 of 22 Jul 12, 2018...
  • Page 16 ISL68300EVAL3Z 3. PCB Layout Guidelines Figure 14. PCB - Bottom Layer (Top View) Figure 15. PCB - Bottom Silk Screen UG173 Rev.0.00 Page 16 of 22 Jul 12, 2018...
  • Page 17: Typical Performance Curves

    ISL68300EVAL3Z 4. Typical Performance Curves Typical Performance Curves Unless noted: V = 12V, T = +25°C (AC-Coupled) 20mV/Div SW_Phase1 5V/Div SW_Phase2 5V/Div Output Current (A) 5µs/Div Figure 16. Efficiency Figure 17. Output Voltage Ripple at Full Load (AC-Coupled) 20mVA/Div (AC-Coupled) 20mV/Div...
  • Page 18: Configuration Files

    5. Configuration files Configuration files Sample configuration files for the ISL68300 in the ISL68300EVAL3Z. Copy and paste (from STORE_CONTROL to ### End User Store) to a text editor and save it as Confile_file_name.txt. The # symbol is used for a comment line.
  • Page 19 ISL68300EVAL3Z 5. Configuration files • Configuration file for the master device (Address = 0x63) STORE_CONTROL 0x21 STORE_CONTROL 0x11 STORE_CONTROL 0x12 # -------------Start of User Settings------------ ON_OFF_CONFIG 0x17 VOUT_COMMAND 0x2000 # 1 V VOUT_CAL_OFFSET 0x0000 # 0 V VOUT_MAX 0x2666 # 1.2 V...
  • Page 20 ISL68300EVAL3Z 5. Configuration files TON_RISE 0xCA80 # 5 ms TOFF_FALL 0xCA80 # 5 ms ISENSE_CONFIG 0x2902 USER_CONFIG 0x0C4A DDC_CONFIG 0x2001 POWER_GOOD_DELAY 0xBA00 # 1 ms ASCR_ADVANCED 0x21A9 INDUCTOR 0xA333 # 0.2 µH OVUV_CONFIG 0x02 # 2 null TEMPCO_CONFIG 0xA7 ASCR_CONFIG...
  • Page 21: Revision History

    ISL68300EVAL3Z 6. Revision History Revision History Rev. Date Description 0.00 Jul 12, 2018 Initial release UG173 Rev.0.00 Page 21 of 22 Jul 12, 2018...
  • Page 22 ISL68300EVAL3Z UG173...

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