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THIS IS THE INPUT MALE HEADER
SDA
SALERT
J1
BI
1
2
SCL
1 2
SGND
3
4
IN
3
4
OUT
5
6
5
6
3P3V
MSTR_EN
OUT
OUT
AGND
IN
AGND
C11
0.1UF
VIN*
1
2
UNNAMED_3_CHOKE_I10_B
OUT
22UH
0.020
L1
R12
AGND
2AUXP
VOUT
ADDR SEL FOR DCP+ PORT EXT
3P3V
1
A0_D
2
OUT
3
SGND
3P3V
1
A1_D
2
OUT
3
SGND
DCP/PORT EXT HAVE THE SAME
BASE SLAVE ADDRESS =0XA0
FREQUENCY_SEL
C15
3P3V
0.1UF
VLOGIC
VCC
GND
RH0
2
UNNAMED_3_ISL23345_I37_RH0
RW0
20
19
RL0
RH1
5
UNNAMED_3_ISL23345_I37_RH1
RW1
4
R13
AGND
3
UNNAMED_3_ISL23345_I37_RL1
RL1
DNP
SDA
SDA
11
SCL
SCL
12
A0 A1 A2
U8
A0_D
U1
R14
C14
AGND
UNNAMED_3_SMCAP_I14_B
1
12
UNNAMED_3_ISL85400_I2_1
TKSS
FS
100K
470PF
2
11
UNNAMED_3_ISL85400_I2_11
SYNC
COMP
VOUT
3
10
UNNAMED_3_ISL85400_I2_3
UNNAMED_3_ISL85400_I2_10
BOOT
FB
R16
120K
4
9
UNNAMED_3_ISL85400_I2_9
VIN
VCC
5
8
PHASE
PG
6
7
REG GAIN
PGND
EN
13
EP
ISL85415
2DAC_OUT
AGND
SMBALERT2
3P3V
1
A0
3
SGND
5
3P3V
1
A1
3
SGND
5
3P3V
1
A2
3
SGND
5
FIGURE 21. SCHEMATIC OF THE ISL28023EVAL2Z BOARD (1 OF 2)
SGND
EP
RH3
16
RW3
17
18
RL3
VIN
INPUT
1
RH2
13
UNNAMED_3_ISL23345_I37_RH2
RW2
AGND
INPUT
14
2
AGND
15
SGND
RL2
SGND
A1_D
C16
SGND
0.1UF
R17
2AUXP
33
R18
2AUXM
33
C17
SGND
0.1UF
SDA
2
4
SCL
6
DRAWN BY:
Ryan Roderick
SDA
2
4
RELEASED BY:
SCL
6
UPDATED BY:
SDA
2
4
SCL
6
THIS IS THE OUTPUT FEMALE HEADER
SDA
J2
1
2
SCL
1 2
3
4
3
4
5
6
5
6
3P3V
VIN*
R20
SGND
0.020
C20
0.1UF
SGND
C22
UNNAMED_3_ISL28023_I1_REGIN
UNNAMED_3_ISL28023_I1_VINM
UNNAMED_3_ISL28023_I1_REGOUT
0.1UF
1
NC1
VCC
18
2
GND1
I2CVCC
17
A2
3
AUXP
A2
16
UNNAMED_3_ISL28023_I1_AUXP
A1
4
AUXM
A1
15
UNNAMED_3_ISL28023_I1_AUXM
isl28023
A0
5
AUXV
A0
14
6
DAC_OUT
GND2
13
EPAD
25
SGND
U9
SCL
SMBALERT2
SDA
SGND
SALERT
DATE:
ENGINEER:
Ryan Roderick
DATE:
TITLE:
ISL28023/ISL854015 Design
DATE:
TESTER
MASK#
SALERT
SGND
MSTR_EN
SGND
3P3V
DATE:
HRDWR ID
REV.
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