IBM 3534-F08 Installation And User Manual page 26

v Eight light-emitting diodes (LEDs) to indicate the status for each port
v Eight LEDs to indicate the link speed for each port
v One LED on the front panel to indicate the overall switch status
v One LED on the back panel to indicate the overall switch status
v Two LEDs for the Ethernet port to indicate the port status and link speed
v Three digital thermometers for temperature sensing
v One 3.3 V to 1.8 V dc/dc converter for the Bloom ASIC core supply
v One Bloom ASIC to support up to eight nonblocking ports
v Eight SERDES
v One real-time clock with a battery
Embedded processor
The embedded processor is an Intel 80960VH processor with a clock speed of 100
MHz. It contains the following components:
v A high-performance RISC processor core (compatible with the 2109 and 3534
v An integrated EDO memory controller (for DRAM, SRAM, read-only memory
v A PCI bus interface
v A complex programmable logic device (CPLD) for SDRAM control
v Two direct memory access (DMA) channels
v An I2C interface
v General purpose I/O
You access system memory through the local bus. The external CPLD SDRAM
device provides SDRAM controller functionality at 33 MHz. It supports parity
checking to enhance the data integrity of the system. The CPU communicates with
the ASIC and the 10BASE-T or 100BASE-T Ethernet media access controller
(MAC) through the PCI interface. An external PCI bus arbiter enables the Ethernet
device to be a bus master.
You can also access the RS232 Universal Asynchronous Receiver Transmitter
(UART) serial port through the local bus. Other I/O peripherals, such as the
real-time clock, the LEDs, the three digital thermometers, and miscellaneous I/O are
handled by the I2C bus of the CPU. The CPU is the only I2C bus master in the
system. The RS232 port and drivers, Ethernet MAC/PHY, and LEDs are external
components to the CPU. An RJ45 connector provides Ethernet connection to
external systems. The DB9 RS232 is a ribbon-cable connection through the
on-board 10-pin header.
Bus operations
The interface between the embedded processor, the ASIC, and the 10BASE-T or
100BASE-T Ethernet MAC is implemented by using a PCI bus. All PCI devices on
the bus are PCI Revision 2.2 compliant. The PCI bus interface operates at 32-bit,
up to 33 MHz and has a worldwide even parity bit. A slave-only PCI interface is
provided by each ASIC to allow the processor to program various registers, routing
tables, and so on within the chip. An external PCI bus arbiter enables the Ethernet
device to be a bus master.
The local bus, a 32-bit multiplexed burst bus, provides the interface between the
system memory and the I/O. Because the integrated EDO memory controller on the
4
IBM TotalStorage SAN Switch: 3534 Model F08 Installation and User's Guide
information
series of switches)
(ROM), and Flash memory)