Denon AVR-X3300W Service Manual page 58

W9864G6KH-5 Block diagram
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
GENER ATOR
RAS
COMMAND
CAS
DECODER
COLUMN DECODER
WE
A10
MODE
A0
REGIST ER
SENSE AMPLIFIER
ADDRESS
A9
BUFFER
A11
BS0
BS1
COLUMN
REFRESH
COUNTER
COUNTER
COLUMN DECODER
SENSE AMPLIFIER
NOTE:
T he cell array configuration is 4096 * 256 * 16
COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #0 BANK #1
SENSE AMPLIFIER
DATA CONTROL DQ
CIRCUIT BUFFER
COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #2 BANK #3
SENSE AMPLIFIER
Publication Release Date: Nov. 12, 2013
- 6 - Revision A02
PCM1690 (HDMI : U1048)
PCM1690 Pin Function
TERMINAL PULL-
I/O
NAME PIN DOWN TOLERANT
RSV2 1 — —
RSV1 2 — —
RSV2 3 — —
RSV1 4 — —
RSV2 5 — —
LRCK 6 I Yes
BCK 7 I Yes
DIN1 8 I No
DIN2 9 I No
DIN3 10 I No
DIN4 11 I No
VDD 12 — —
DGND 13 — —
SCKI 14 I No
RST 15 I Yes
ZERO1 16 O No
ZERO2 17 O No
AMUTEI 18 I No
AMUTEO 19 O No
MD/SDA/DEMP 20 I/O No
MC/SCL/FMT 21 I No
MS/ADR0/RSV 22 I Yes
TEST/ADR1/RSV 23 I/O No
58
5-V
DESCRIPTION
— Reserved, tied to analog ground
— Reserved, left open
— Reserved, tied to analog ground
— Reserved, left open
— Reserved, tied to analog ground
No Audio data word clock input
No Audio data bit clock input
No Audio data input for DAC1 and DAC2
No Audio data input for DAC3 and DAC4
No Audio data input for DAC5 and DAC6
No Audio data input for DAC7 and DAC8
— Digital power supply, +3.3 V
— Digital ground
Yes System clock input
Yes Reset and power-down control input with active low
No Zero detect flag output 1
No Zero detect flag output 2
Yes Analog mute control input with active low
Yes Analog mute status output(1) with active low
Input data for SPI, data for I2C(1), de-emphasis
Yes
control for hardware control mode
Clock for SPI, clock for I2C, format select for hardware
Yes
control mode
Chip Select for SPI, address select 0 for I2C, reserve
Yes
(set low) for hardware control mode
Test (factory use, left open) for SPI, address select 1
Yes
for I2C, reserve (set low) for hardware control mode