Clock Generation; Pll And Jitter Attenuation; Figure 9. Cs42528 Clock Generation - Cirrus Logic CDB42528 Manual

114 db, 192 khz 8-ch codec with s/pdif receiver
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4.5

Clock Generation

The clock generation for the CS42528 is shown in the figure below. The internal MCLK is derived from the
output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of
PLL lock to the other source input.
Recovered
S/PDIF Clock
0
SAI_LRCK
(slave mode)
1
PLL_LRCK bit
OMCK
4.5.1

PLL and Jitter Attenuation

An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming S/PDIF data stream.
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is im-
portant. For this reason, the PLL has been designed to have good jitter attenuation characteristics as
shown in Figure 28 on page 81.
The PLL can be configured to lock onto the incoming SAI_LRCK signal from the Serial Audio Interface
Port and generate the required internal master clock frequency. By setting the PLL_LRCK bit to a '1' in
the register "Clock Control (address 06h)" on page 53, the PLL will lock to the incoming SAI_LRCK and
generate an output master clock (RMCK) of 256Fs. Table 2 shows the output of the PLL with typical input
Fs values for SAI_LRCK.
See "Appendix C: PLL Filter" on page 80 for more information concerning PLL operation, required filter
components, optimal layout guidelines and jitter attenuation characteristics.
DS586PP5
X2
Internal
MCLK
00
PLL (256Fs)
Auto Detect
8.192 -
Input Clock
49.152 MHz
1,1.5, 2, 4
01
SW_CTRLx bits
(manual or auto
switch)

Figure 9. CS42528 Clock Generation

RMCK_DIVx bits
00
2
01
10
4
single
11
speed
256
double
speed
128
quad
speed
64
single
speed
4
double
speed
2
quad
speed
1
CS42528
RMCK
00
01
CX_LRCK
10
CODEC_FMx bits
DAC_OLx
00
or ADC_OLx bits
01
10
not OLM
128FS
CX_SCLK
OLM #1
256FS
OLM #2
00
01
SAI_LRCK
10
SAI_FMx bits
ADC_OLx and
00
ADC_SP SELx bits
01
10
not OLM
128FS
SAI_SCLK
OLM #1
256FS
OLM #2
25

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