Table 22. Revision History - Cirrus Logic CDB42528 Manual

114 db, 192 khz 8-ch codec with s/pdif receiver
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Release
Date
A1
December 2002
PP1
August 2003
PP2
August 2003
PP3
March 2004
PP4
July 2004
PP5
January 2005
90

Table 22. Revision History

Advance Release
Preliminary Release
– Added Revision History table.
– Updated registers 6.7.4 and 6.7.5 on page 54.
Corrected error in document title.
Add lead free part numbers
– Updated PLL components in Table 21 on page 81.
– Added PDN_RCVR1 bit and description on page 48.
Added LOCKM bit and description on page 66.
Added OMCK Frequency specification in the Switching Characteristics table on
page 12.
Updated ADC Input Impedance and Offset Error specifications in the Analog
Input Characteristics table on page 8.
Updated the DAC Full Scale Voltage, Output Impedance, and Gain Drift
specifications in the Analog Output Characteristics table on page 10.
Updated specification conditions for the analog input characteristics on page 8.
Updated specification conditions for the analog output characteristics on
page 10.
Updated specification of t
page 12.
Corrected reference to the SW_CTRL[1:0] bits in section 4.5.3 on page 26.
Moved the VQ and FILT+ specifications from the Analog Input Characteristics
table on page 8 to the DC Electrical Characteristics table on page 15.
– Updated the Power Supply Current and Power Consumption specifications in
the DC Electrical Characteristics table on page 15.
– Updated the description of the CONF bit on page page 68.
– Updated Table 13 on page 55 to include HDCD format detection.
– Corrected default value of the Chip_ID[3:0] bits in register 01h on pages 42 and
47.
– Updated default value of the Rev_ID[3:0] bits in register 01h on pages 42 and
47.
Changes
and t
in the Switching Characteristics table on
ds
dh
CS42528
DS586PP5

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