Sony WLL-CA55 Maintenance Manual page 90

IC
CXD9152R (SONY)
OFDM MODULATOR
—TOP VIEW—
157
160
165
170
175
180
185
190
195
200
205
208
PIN PIN
I/O SIGNAL I/O
NO. NO.
I EXT CLK27
1 I 53 O
2 I I DATA ENABLE 54 O
D.GND
3 — 55 O
4 — NC 56 O
A.GND
5 — 57 O
6 — A.V 58 O
CC
7 O O OFDM SIGNALX 59 O
O OFDM SIGNAL
8 O 60 —
9 — A.V 61 —
CC
A.GND
10 — 62 O
11 O IO VRO 63 O
I VREF
12 I 64 O
13 O O COMP 65 O
NC
14 — 66 O
15 — D.GND 67 O
CLK MASTER 18M
16 I 68 O
17 I RST 69 O
18 I I TCK 70 O
D.VCC
19 — 71 O
20 I I TRST 72 —
I TDI
21 I 73 —
22 I I TMS 74 O
O TDO
23 O 75 O
24 I I PLL RST 76 O
I PLL A
25 I 77 O
26 — A.GND 78 —
A.V
27 — CC 79 —
28 I I TS DATA7 80 O
29 — NC 81 O
I TS DATA6
30 I 82 O
31 I I TS DATA5 83 O
I TS DATA4
32 I 84 O
33 I I TS DATA3 85 —
D.V
34 — CC 86 —
35 I I TS DATA2 87 O
I TS DATA1
36 I 88 O
37 I I TS DATA0 89 O
GND
38 — 90 O
39 — D.V 91 O
CC
40 O O CLK 9M 92 O
O PREQ
41 O 93 O
42 O O TEST OUT0 94 O
D.V
43 — CC 95 O
44 O O TEST OUT1 96 —
O TEST OUT2
45 O 97 —
46 O O TEST OUT3 98 O
O TEST OUT4
47 O 99 O
48 O O TEST OUT5 100 O
O TEST OUT6
49 O 101 O
50 — D.GND 102 O
O TEST OUT7
51 O 103 O
O TEST OUT8
52 O 104 O
4-4
PIN PIN
SIGNAL I/O SIGNAL I/O
NO. NO.
O TEST OUT9 O TINT ADRS7
105 O 157 I
O TEST OUT10 106 O O TINT ADRS6 158 I
O TEST OUT11 D.GND
107 — 159 I
O TEST OUT12 108 O O TINT ADRS5 160 I
O TEST OUT13 O TINT ADRS4
109 O 161 I
O TEST OUT14 110 O O TINT ADRS3 162 I
O TEST OUT15 O TINT ADRS2
111 O 163 I/O
D.GND O TINT ADRS1
112 O 164 —
D.V 113 O O TINT ADRS0 165 —
CC
O TEST OUT16 D.V
114 — CC 166 I/O
O R OOS 115 I/O IO TINT DATA5 167 I
O R OVERFLOW IO TINT DATA4
116 I/O 168 I
O R EARLY PCR 117 I/O IO TINT DATA3 169 I
O IFTSO3 IO TINT DATA2
118 I/O 170 I
O IFTSO2 119 — D.GND 171 I
O IFTSO1 IO TINT DATA1
120 I/O 172 I
O IFTSO0 121 I/O IO TINT DATA0 173 I
O DA CLK O TINT CS
122 O 174 I
O DIGIT DT11 D.V
123 — CC 175 I
D.GND 124 O O TINT OE 176 —
D.V O TINT WE
CC 125 O 177 —
O DIGIT DT10 126 O O IIC ERR 178 I
O DIGIT DT9 O NOE
127 O 179 I
O DIGIT DT8 128 O O INTR 180 I
O DIGIT DT7 O NRD
129 O 181 I
D.V 130 — D.GND 182 I
CC
D.V D.V
CC 131 — CC 183 —
O DIGIT DT6 132 O O NWR 184 I
O DIGIT DT5 O PLL LOCK
133 O 185 I
O DIGIT DT4 I TEST IN24
134 I 186 I
O DIGIT DT3 135 I I TEST IN23 187 I
O DIGIT DT2 I TEST IN22
136 I 188 I
D.V 137 I I TEST IN21 189 —
CC
D.V D.V
CC 138 — CC 190 —
O DIGIT DT1 139 I I TEST IN20 191 I
O DIGIT DT0 I TEST IN19
140 I 192 I
O TINT ADRS21 141 I I TEST IN18 193 I
O TINT ADRS20 D.GND
142 — 194 I
O TINT ADRS19 143 I I TEST IN17 195 I
O TINT ADRS18 I TEST IN16
144 I 196 I
O TINT ADRS17 I TEST IN15
145 I 197 I
O TINT ADRS16 146 I I TEST IN14 198 —
O TINT ADRS15 D.V
147 — CC 199 I
D.V 148 I I TEST IN13 200 —
CC
D.V I TEST IN12
CC 149 I 201 —
O TINT ADRS14 150 I I TEST IN11 202 I
O TINT ADRS13 I TEST IN10
151 I 203 —
O TINT ADRS12 152 I I TEST IN9 204 I/O
O TINT ADRS11 I TEST IN8
153 I 205 I
O TINT ADRS10 154 — D.GND 206 O
O TINT ADRS9 I TEST IN7
155 I 207 I
O TINT ADRS8 I TEST IN6
156 I 208 I
INPUTS
CLK MASTER 18M
I CLK18 TEST
I CLK36 TEST
104
I CLK73 TEST
I CLK9 TEST
100
I DATA ENABLE
I EA
95 I EXT CLK27
I EXT CLOCK EN
I IIC CCR0 - I IIC CCR4
90
I IIC PARA MODON
I IIC SLAVE A0 - I IIC SLAVE A6
85 I IIC SLEEP
I IIC TEST
I INP BUSCNT0 - I INP BUSCNT3
80
I OUT BUSCNT0 - I OUT BUSCNT2
I OUT MUTE
75
I PLL A
I PLL RST
I TCK, I TDI, I TMS, I TRST
70
I TEST IN0 - I TEST IN24
I TS DATA0 - I TS DATA7
65
I VREF
I XTAL A, I XTAL C
RST
60
OUTPUTS
55
IO VRO
53
O CLK 9M
O COMP
O DA CLK
O DIGIT DT0 - O DIGIT DT11
O IFTSO0 - O IFTSO3
O IIC ERR
O INTR
O NOE
O NRD
SIGNAL
O NWR
I TEST IN5 O OFDM SIGNAL,
I TEST IN4 O OFDM SIGNALX
I TEST IN3
O PLL LOCK
I TEST IN2
O PREQ
I TEST IN1
O R EARLY PCR
I TEST IN0
O R OOS
IO IIC CLK
O R OVERFLOW
D.GND
O TDO
D.V
CC
O TEST OUT0 - O TEST OUT16
IO IIC DATA
O TINT ADRS0 - O TINT ADRS21
I IIC SLEEP
I IIC PARA MODON O TINT CS
I IIC CCR4
O TINT OE
I IIC CCR3
O TINT WE
I IIC CCR2
O XTAL 18M
I IIC CCR1
I IIC CCR0
INPUTS/OUTPUTS
I IIC TEST
IO IIC CLK
I CLK73 TEST
IO IIC DATA
D.GND
IO TINT DATA0 - IO TINT DATA5
D.V
CC
I EXT CLOCK EN IO XTAL EB
I OUT MUTE
I INP BUSCNT3
I INP BUSCNT2
I INP BUSCNT1
D.V
CC
I INP BUSCNT0
I OUT BUSCNT2
I OUT BUSCNT1
I OUT BUSCNT0
I CLK36 TEST
D.GND
D.V
CC
I CLK18 TEST
I EA
I IIC SLAVE A6
I IIC SLAVE A5
I IIC SLAVE A4
I IIC SLAVE A3
I IIC SLAVE A2
NC
I CLK9 TEST
D.GND
D.V
CC
I XTAL A
D.V
CC
IO XTAL EB
I XTAL C
O XTAL 18M
I IIC SLAVE A1
I IIC SLAVE A0
: MASTER CLOCK FOR PLL (18.28 MHz)
: EXTERNAL CLOCK (18 MHz)
: EXTERNAL CLOCK (36 MHz)
: EXTERNAL CLOCK (73 MHz)
: EXTERNAL CLOCK (9 MHz)
: DATA ENABLE
: INPUT BUFFER POWER CONTROL
: EXTERNAL CLOCK
: EXTERNAL CLOCK ENABLE
: IIC CLOCK RATE CONTROL
: IIC PARALLEL WRITE/READ MODE
: IIC CONTROLLED ADDRESS
: IIC SLEEP
: IIC TEST MODE
: TEST INPUT CONTROL
: TEST OUTPUT CONTROL
: OUTPUT MUTING CONTROL
: PLL THROUGH CLOCK
: PLL RESET
: TEST
: TEST DATA
: TS DATA
: REFERENCE VOLTAGE (1.1 V)
: CRYSTAL OSCILLATOR
: POWER ON RESET
: CONNECTION OF RESISTANCE
: CLOCK (9 MHz)
: TEST
: CLOCK FOR EXTERNAL D/A CONVERTER (36 MHz)
: DIGITAL DATA
: INVERSE FAST FOURIER TRANSFORM
: IIC ERROR
: IIC INTERRUPT
: IIC VALID
: IIC READ
: IIC WRITE
: ANALOG OFDM SIGNAL
: PLL LOCK SIGNAL
: PACKET REQUEST
: PROGRAM CLOCK REFERENCE DEJITTER OVERFLOW
: TS DATA OUT OF SYNC
: FIFO OVERFLOW
: TEST
: TEST DATA
: SRAM ADDRESS
: SRAM CHIP SELECT
: SRAM OUTPUT ENABLE
: SRAM WRITE ENABLE
: CRYSTAL OSCILLATOR (18 MHz)
: IIC SERIAL CLOCK
: IIC SERIAL DATA
: SRAM DATA
: CRYSTAL OSCILLATOR
WLL-CA55