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Local Bus to DRAM Cycle Times
The DRAM base address, array size, and device size are programmable. The
DRAM controller assumes an interleaved architecture if the DRAM size
requires eight physical devices (that is, when memory array size is 4MB and
DRAM technology is 4 Mbits per device; or when memory array size is 16MB
and DRAM technology is 16 Mbits per device.)
Parity checking and parity exception action is also programmable. The DRAM
array size and device size are initialized in the DRAM Space Size Register.
Clock Budget
4,2,2,2
4,1,1,1
5,3,3,3
5,2,2,2
3,2,2,2
5,3,3,3
5,2,2,2
6,4,4,4
6,3,3,3
4,2,2,2
N
TEA is the MC68040 bus error transaction signal. "With TEA"
ote
indicates that a bus error cycle occurs if a DRAM parity error was
detected.
EPROM/Flash Cycle Times
The EPROM/Flash cycle time is programmable from 3 to 10 bus clocks/byte
(4 bytes = 12 to 40). (The actual cycle time may vary depending on the device
speed.) The data transfers are 32 bits wide. Refer to the MVME162 Embedded
Controller Programmer's Reference Guide.
SCSI Transfers
The MVME162 includes an SCSI mass storage bus interface with DMA
controller. The SCSI DMA controller uses a FIFO buffer to interface the 8-bit
SCSI bus to the 32-bit local bus. The FIFO buffer allows the SCSI DMA
controller to efficiently transfer data to the local bus in four longword bursts.
MVME162/D2
Table 4-1. DRAM Performance
Operating Conditions
Non-interleaved, read, 25 MHz, without TEA on parity error
Interleaved, read, 25 MHz, without TEA on parity error
Non-interleaved, read, 25 MHz, with TEA on parity error
Interleaved, read, 25 MHz, with TEA on parity error
Write, 25 MHz
Non-interleaved, read, 33 MHz, without TEA on parity error
Interleaved, read, 33 MHz, without TEA on parity error
Non-interleaved, read, 33 MHz, with TEA on parity error
Interleaved, read, 33 MHz, with TEA on parity error
Write, 33 MHz
MVME162 Functional Description
4
4-11
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