Table 3-1. Local Bus Memory Map - Emerson Motorola MVME162 User Manual

Operating Instructions
3
Address Range
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
$FF800000-$FF9FFFFF
$FFA00000-$FFBFFFFF
$FFC00000-$FFCFFFFF
$FFD00000-$FFDFFFFF
$FFE00000-$FFE7FFFF
$FFE80000-$FFEFFFFF
$FFF00000-$FFFEFFFF
$FFFF0000-$FFFFFFFF
N
otes
3-4

Table 3-1. Local Bus Memory Map

Devices Accessed
DRAM on Board
SRAM
VMEbus A32/A24
IP_a Memory
IP_b Memory
IP_c Memory
IP_d Memory
Flash/EPROM
EPROM/Flash
Not Decoded
Not Decoded
SRAM default
Not Decoded
Local I/O Devices
(Refer to next table)
VMEbus A16
1. Reset enables the decoder for this space of the memory map so
that it will decode address spaces $FF800000 - $FF9FFFFF and
$00000000 - $003FFFFF. The decode at 0 must be disabled in
the MCchip before DRAM is enabled. DRAM is enabled with
the DRAM Control Register at address $FFF42048, bit 24.
PROM/Flash is disabled at the low address space with PROM
Control Register at address $FFF42040, bit 20.
2. This area is user-programmable.
decoder is programmed in the MCchip, the local-to-VMEbus
decoders are programmed in the VMEchip2, and the IP
memory space is programmed in the IPIC.
3. Size is approximate.
4. Cache inhibit depends on devices in area mapped.
Port Width Size
D32 1MB-8MB
D32 128KB-2MB
D32/D16 --
D32-D8 64 KB-8 MB
D32-D8 64 KB-8 MB
D32-D8 64 KB-8 MB
D32-D8 64 KB-8 MB
D32 2 MB
D32 2 MB
D32 1 MB
D32 1 MB
D32 512 KB
-- 512 KB
D32-D8 878 KB
D32/D16 64 KB
The DRAM and SRAM
Software
Cache Notes
Inhibit
N 2
N 2
? 4
? 2, 4
? 2, 4
? 2, 4
? 2, 4
N 1, 5
N 6
N 7
N 7
N --
N 7
Y 3
? 2, 4
User's Manual